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EXAMPLE: Ring_Oscillator_Extraction

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Extraction ,Layout ,Inets ,Vtime ,VSpec ,Connectivity_Checker

Design Notes

iNet Parasitic Extraction Basics

The AWR Design Environment allows a powerful methodology for including net parasitics in your simulation. Once you have implemented an intelligent net (iNet), you can simulate the circuit with its affects, even if the rest of the circuit' s layout is not. Parasitic extractions can also be done in groups, which allows you to break up the extraction problem into smaller problems or use different physical simulators.

This example will demonstrate the basics of including the parasitics from iNets in simulation results.


This example is a three stage ring oscillator with a completed layout. iNets are used to wire up the circuit for both the signal path and the power supply rails. The Net-An parasitic extractor will be used to generate the parasitics for the iNets. The signal path will be setup to generate a RLCK extraction while the power supply rails will be setup to only generate an R extraction.

The schematic " Ring Oscillator" is the complete design; you can view the layout to see device pcells are wired together with iNets. The graph " Spectrum" shows the frequency domain spectral results, " Supply_Voltages" shows the time domain waveforms at the source of each of the PMOS devices, and " Waveform" shows the time domain waveforms at the output of the circuit. There is a capacitor at the output of the design. It is set to 0 pF to show the shift in frequency due to only the parasitics of the iNets.

When you first simulate this project, the iNet parasitics have not been simulated.

Schematic - Ring_Oscillator

Schematic Layout - Ring_Oscillator

Graph - Spectrum

Graph - Waveform

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