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What's New in AWRDE V14

NI AWR Design Environment v14.02 Edition


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© 2019 National Instruments. All rights reserved. © 2019 AWR Corporation. All rights reserved.

Trademarks

  • Analog Office, APLAC, AWR, AWR Design Environment, AXIEM, Microwave Office, National Instruments, NI, ni.com and TX-Line are registered trademarks of National Instruments. Visual System Simulator (VSS), Analyst, and AWR Connected are trademarks of AWR Corporation/National Instruments. Refer to the Trademarks section at ni.com/trademarks for other National Instruments trademarks.

  • Other product and company names mentioned herein are trademarks or trade names of their respective companies.

Patents

For patents covering NI AWR software products/technology, refer to ni.com/patents.

The information in this guide is believed to be accurate. However, no responsibility or liability is assumed by National Instruments for its use.


Table of Contents

NI AWR Design Environment (NI AWRDE) 14 What's New
What's New Organization
Major Feature Overview
V14 Licensing And Operating System Changes
NI AWR Design Environment (NI AWRDE)
Microwave Office and Analog Office
Visual System Simulator (VSS)
Analyst 3D Editor
NI AWR Design Environment (NI AWRDE) Features
AWR and Analyst Installer
Enhanced Data Processing and Display
Measurement Variables
Document Sets
DOC_SET
Data Source Group
Window-in-window Insertion and Alignment
Updated Tuner and Element Options Dialog Boxes
AntSyn Antenna Synthesis
Phased Array Generator Wizard
Scripting Resources
Minor Improvements
API
Data Sets
Environment
Graphs
Output Files
User Interface
Microwave Office (MWO) and Analog Office Features
Network Synthesis Wizard
Plotting Measurements Versus Output Power, Voltage, or Current
Power Amplifier and Load Pull
PCB Import Wizard Enhancements
iNet Enhancements
LPF LineType Editing
APLAC Loop Gain Analysis
Updated Layout Manager
EM Editor Improvements
EM Point Ports
Relocating Edge Ports
Adding Ports
Inserting and Deleting Dielectric Layers
AXIEM Performance
Analyst Performance
Analyst Options
Per Material Solve Inside Conductors
Per Shape Mesh Control
Analyst Internal Wave Ports
Analyst Frequency-dependent Materials
Analyst 3D Editor
Minor Improvements
New/Updated Examples
New Circuit Models
New Circuit Measurements
Linear Measurements
Load Pull Measurements
Stability Measurements
New Scripts
API
Equations
Layout
Layout - EM
Layout - Import/Export
Libraries
Measurements
Models
Remote Computing
Scripts
Simulation - APLAC
Simulation - Circuit Envelope
Simulation - AWR Connected EM Partners
Tuning, Yield Analysis and Optimization
User Interface
Verification
Wizard - PCB Import
Visual System Simulator (VSS) Features
Phased Array and MIMO Systems
Large Element Count Performance Improvements
Spatial Channel Model
Phased Array Generator Wizard
Bus Support
LDPC Encoder/Decoder
5G, NB-IoT and LTE Standards
Minor Improvements
New/Updated Examples
New System Blocks
Bus Support
Channel Encoding
Communication Standards
Math Tools
RF Blocks
Spatial Channel Model
New System Measurements
RF Budget Measurements
Spectrum Measurements
Measurements
Output Files
Simulation
System Block Updates
System Diagrams
Analyst 3D Editor Features
Environment
Variables
Choice and File Variables
Multiple Selection Improvements
Parameter References
Color Parameter Access
High-DPI (4k)
Units
Project Performance
Geometry
Performance
View Clip Planes
Edge Translation
Edge Query Improvements
Minimum Distance Between Entities
Visualization Quality
User Folder Order
Text Solid
Planar Body Wrapping
Sheet Body Thickening
Open Shell Sweeps
Camera
Align to Faces
Mouse-Driven Fit
Smooth Transitions
Attributes
Material Assignment Count Indicator
Preferences
Zoom-To
Remove All Applications
Version 14.02 Updates
API
Cell Libraries
Data Sets
Design Notes
Equations
Geometry Simplification (SPP) Rules
Graphs
Layout
Layout - EM
Layout - Shape Modifiers
Libraries
Measurements - Systems
Models - Circuit
Models - System
Project Import
Schematic Editor
Scripts
Simulation - Analyst
Simulation - APLAC
Simulation - AXIEM
Simulation - SPICE
Simulation - System
Symbol Editor
Tuning, Yield Analysis and Optimization
User Interface
Wizards - Create New Process
Wizards - IFF Import and Export
Wizards - PCB Import
Wizards - Phased Array Generator
Wizards - PHD Model Generation Wizard
Version 14.01 Updates
New Examples
API
Cell Libraries
Data Sets
DRC/LVS - Interface
Geometry Simplification (SPP) Rules
Graphs
Job Scheduler
Layout
Layout - EM
Load Pull
Measurements - Circuit
Models - System
Schematic Editor
Shape Modifiers
Simulation - Analyst
Simulation - AWR Connected EM Partners
Simulation - APLAC
Simulation - AXIEM
Simulation - Extraction
Simulation - Systems
Symbol Editor
Tuning, Yield Analysis and Optimization
User Interface
Wizards - Network Synthesis
PCB Import
Wizards - Create New Process
Migration Issues
NI AWRDE V14 Specific Migration Issues
Licensing Changes
Licensing
HASP4 Hardware Dongle
Remote EM Computing
Synthesis Wizards
Analyst-MP Driven Frequency and Eigenmode Solvers
Operating System
Artwork Cell Export Options
Layout Boolean Option
Data Source Group User Folders
5G System Blocks
Remote Computing Version Compatibility
Version-Independent Migration Issues
Files Automatically Migrated
Files in Appdatacommon
Files in Appdatauser
Files NOT Automatically Migrated
License File
User-Defined XML Libraries
Other Concerns
Model Compatibility
Multiple NI AWRDE Versions
Redirection

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