Go to www.awrcorp.com
Back to search page Click to download printable version of this guide.

What's New in AWR Design Environment v16

© 2021 Cadence Design Systems, Inc. All rights reserved.
Printed in the United States of America.

Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA.

Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission.

Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522.

All other trademarks are the property of their respective holders.

Restricted Permission:This publication is protected by copyright law and international treaties and contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to print one (1) hard copy of this publication subject to the following conditions:

  1. The publication may be used only in accordance with a written agreement between Cadence and its customer.

  2. The publication may not be modified in any way.

  3. Any authorized copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement.

  4. The information contained in this document cannot be used in the development of like products or software, whether for internal or external use, and shall not be used for the benefit of any other party, whether or not for consideration.

Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information.

Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

Table of Contents

AWR Design Environment V16 What's New
What's New Organization
Major Features Overview
Limited Release Features
AWR Design Environment
Microwave Office
AWR Design Environment V16 Licensing and Operating System Changes
AWR Design Environment Features
Improved Python Interface
Version Control Integration
Microwave Office Features
Dynamic Voiding, Smoothing, and Automatic Net Connectivity Extraction
Robust Simplex Optimizers
Multi-Version Process Library (PDK) Support
Job Scheduler Enhancements
Parallel and Remote Circuit Simulation
Remote Linux EM Simulations
AXIEM Data Set Size Reduction
Analyst Simulator Improvements
Interoperability with Allegro and Virtuoso Platforms
Clarity 3D Solver Integration
Celsius Thermal Solver Integration
Minor Improvements
New Circuit Models
Coplanar Elements
Microstrip Components
Interconnects and Lumped Elements
New Circuit Measurements
Linear Measurements
Output File Measurements
Cell Libraries
Job Scheduler
Layout - EM
Output Equations
Schematic Editor
Simulation - APLAC
User Interface
VSS (VSS) Features
Layout Trace Interconnect Modeling
RF Amplifier Power Saturation Improvements
Frequency Multiplier Amplitude and Spur Level Improvements
APSK Modulation
New LDPC Encoding Schemes
Minor Improvements
New/Updated Examples
New/Updated System Blocks
Simulation Control
New System Measurements
RF Budget Measurements
System Eye Diagram Measurements
System Block Updates
Version 16.01 Updates
Cadence Unified Library
Celsius Interoperability
Clarity Interoperability
Data Sets
Job Scheduler
Layout - EM
Measurements - Circuit
Schematic Editor
Simulation - Analyst
Simulation - APLAC
Simulation - Linear
Simulation - RF Budget
Simulation - Systems
Tuning, Yield Analysis and Optimization
User Interface
Wizards - PCB Import
Wizards - Stability Analysis using STAN
Migration Issues
AWR Design Environment V16 Specific Migration Issues
Licensing Changes
Operating System
AXIEM Data Sets
Job Scheduler Remote Execution Options
Process Libraries
Version-Independent Migration Issues
Files Automatically Migrated
Files in Appdatacommon
Files in Appdatauser
Files NOT Automatically Migrated
User-Defined XML Libraries
Other Concerns
Model Compatibility
Multiple AWR Design Environment Software Versions

Legal and Trademark Notice