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AWR VSS (VSS) Features

The Cadence® AWR® Visual System Simulator™ (VSS) communications and radar systems design version 15 software includes the following new features, enhancements, and user interface changes. The Cadence® AWR Design Environment® platform changes also apply to these specific products.

5G NR Library

The 5G NR library contains TX and RX functionality for Downlink and Uplink modes. It supports FR1 and FR2 frequency bands and configurations. A number of test benches are included as examples to jump-start the component design and evaluation process with pre-configured TX and RX blocks, as well as measurements. Test Model configurations defined in the 5G NR specifications are also included in the library, along with a complete set of corresponding test benches.



The PHARRAY_F block now supports buses. This is available when operating in MIMO mode. Buses may be used on either or both the circuit and the radiated sides of the array assembly. The CKTSIGTYP parameter is used to configure the circuit side and the RADSIGTYP parameter is used to configure the radiated side. The use of buses is recommended over the use of multiplexed signals, as more comprehensive RF modeling can be performed with buses.

Additional Information:

VSS Amplifier Model Updates

Updates to the AWR VSS software nonlinear amplifier blocks as well as the AWR VSS software linear blocks LIN_F2 and LIN_MDIF include:

  • The NL_F block is replaced with the AMP_F block.

  • Interpolation between independent variables is now supported for the data file blocks AMP_F, NL_MDIF, LIN_F2, and LIN_MDIF.

  • NL_S support of interpolation between the independent variables of the co-simulated schematic.

  • Extrapolation from the input power levels is now pinned to the lower power level.

  • The algorithm used to generate the polynomial coefficients from PIn/POut curves in AMP_F/NL_F now presumes the lowest PIn corresponds to linear gain and therefore gives more weight to matching the linear gain of the polynomial with the gain of the lowest PIn entry.

  • If the FLTRIMPL parameter of the nonlinear amps is explicitly set to "FIR" then the impedance mismatch filters now also use FIR filtering.

  • Nonlinear amplifiers in Time Domain simulations now calculate their impedances similar to RFB/RFI. This primarily affects impedances when there is S12 in the nonlinearity.

  • The DFTYP parameter is removed from NL_F.

Digital Pre-Distortion

The new digital pre-distortion (DPD) block offers several linearization algorithms that can be used to linearize nonlinear amplifiers. Supported models include memory polynomial, generalized memory polynomial, dynamic deviation reduction of 2nd order (DDR2), and look-up table. Solver choices include least-squares and damped Newton algorithms.

Analog-to-Digital Converter Update

The new ADC2 block implements an ideal sample and hold analog-to-digital converter (ADC). This model utilizes an adjustable threshold vector to convert input samples into digital symbols. Nonlinear distortions found in an analog-to-digital converter may be simulated by varying this threshold vector. ADC2 generates both, the digital and the quantized signals.

Additional Information:

Minor Improvements

AWR VSS v15 software includes the following minor new features, enhancements, and user interface changes:

New/Updated Examples

The following are new or updated AWR Design Environment platform examples for v15. To find an example, choose File > Open Example and type the example name.

  • Downlink TX test bench: 5G_NR_DL_TX_Testbench.emp

  • Downlink RX test bench: 5G_NR_DL_RX_Testbench.emp

  • Uplink TX test bench: 5G_NR_UL_TX_Testbench.emp

  • Uplink RX test bench: 5G_NR_UL_RX_Testbench.emp

  • 5G_NR_FR1_TM1_1.emp

  • 5G_NR_FR1_TM1_2.emp

  • 5G_NR_FR1_TM2.emp

  • 5G_NR_FR1_TM2a.emp

  • 5G_NR_FR1_TM3_1.emp

  • 5G_NR_FR1_TM3_1a.emp

  • 5G_NR_FR1_TM3_2.emp

  • 5G_NR_FR1_TM3_3.emp

  • 5G_NR_FR2_TM1_1.emp

  • 5G_NR_FR2_TM2.emp

  • 5G_NR_FR2_TM3_1.emp

  • ADC: ADC.emp

  • AMP_F_Frequency_Dependence: AMP_F_Frequency_Dependence.emp

  • AMP_F_Test_Benches: AMP_F_Test_Benches.emp

  • Cascade_Damage: Cascade_Damage.emp

  • Chirp_Radar_System: Chirp_Radar_System.emp

  • Coffee_Can_Radar: Coffee_Can_Radar.emp

  • Diplexer: Diplexer.emp


  • Filter_Bank: Filter_Bank.emp

  • IF_Subsampling_ADC: IF_Subsampling_ADC.emp

  • LTE_DL_FDD_RX_TestBench: LTE_DL_FDD_RX_TestBench.emp

  • LTE_DL_FDD_TX_TestBench: LTE_DL_FDD_TX_TestBench.emp

  • LTE_DL_TDD_TX_TestBench: LTE_DL_TDD_TX_TestBench.emp

  • LTE_UL_FDD_RX_TestBench: LTE_UL_FDD_RX_TestBench.emp

  • Phased_Array: Phased_Array.emp

  • Phased_Array_Generator: Phased_Array_Generator.emp

  • Pulse_Doppler_Radar_System: Pulse_Doppler_Radar_System.emp

  • Pulse_Doppler_Radar_System_Matlab: Pulse_Doppler_Radar_System_Matlab.emp

New/Updated System Blocks

The following new system blocks are included in AWR VSS v15 software.

Amplifier Model

AMP_F is updated to support all file formats, including all the capabilities previously included only in the NL_F block.

Frequency Controlled Switch

RFSW_FRQ is a frequency-controlled RF switch that can be useful in building filter banks.

New System Measurements

The following new system measurements are included in AWR VSS v15 software.


  • RF Budget Analysis noise-based measurements and Time Domain spectrum-based measurements now support the specification of a measurement noise floor.

System Block Updates

  • The Element Options dialog box Filter Design tab for the AWR VSS software Filters such as BPFC and LPFB now includes a button that centers the frequency range displayed using the edges of the filter.

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