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Cadence® Microwave Office® software V16 includes the following new features, enhancements, and user interface changes. The Cadence AWR Design Environment® platform changes also apply to these specific products.
A new dynamic voiding layout mode automatically analyzes the layout and generates the clearance between layout shapes and nets. For RF PCB applications, you can dynamically generate ground floods using Allegro-based voiding and smoothing algorithms, and easily run EM analysis on the voided and smoothed layout within the AWR Design Environment platform.
The clearance spacing between layout shapes and nets for various drawing layers is defined by constraint rules specified in the layout process file (LPF).
The new Net and Constraint View window allows you to easily manage nets. You can quickly browse and filter among the various net objects in the selected schematic. You can assign net names and constraint sets to signal traces and dynamic shapes for use in dynamic voiding. Additionally, you can highlight in both the Schematic and Layout Views instances and shapes associated with a selected net.
A new automatic net connectivity mode eliminates the need to manually select and associate shapes with nets. Shapes that overlay signal traces automatically inherit the net name of the signal trace.
Additional Information:
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Documentation: “Dynamic Voiding”.
A new single-thread Robust Simplex optimizer and a Parallel Robust Simplex optimizer are introduced in this release. The new optimizers have an improved algorithm and are more flexible than current Simplex optimizers. They are more widely applicable and/or resistant to local minima. The parallel version can more thoroughly search the design space, therefore is even more robust to local minima.
Additional Information:
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Documentation: “Optimization Methods”.
You can now design and simulate complex RF systems with IP from multiple versions of the same PDK within the same project. Global Definitions and LPF associations automatically update when changing PDK versions.
Additional Information:
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Documentation: “Working With Foundry Libraries”.
The Job Scheduler now supports enabling multiple remote queues simultaneously. Additionally, EM structures now support per-document remote queue selection. Possible setups include separate queues for Windows and Linux jobs, or separate Linux queues with different submit options.
Additional Information:
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Documentation: “Utilizing Remote Computing”.
Parallel and remote circuit simulation enables multiple Microwave Office software simulations to run simultaneously on the same computer, or remotely in parallel on multiple computers in a simulation queue. Long simulations, such as complex harmonic balance simulations, linear simulations involving extremely large S-parameters, parameter sweeps, load pull simulations, optimization, and yield analysis may benefit from a significant reduction in simulation time when run in parallel.
Additional Information:
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Documentation: “Remote and Parallel Simulation ”.
You can now run AXIEM and Analyst simulations from the AWR Design Environment platform on a remote Linux cluster.
Additional Information:
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Documentation: “Remote Linux Simulations”.
A new Store De-embedding Network option allows you to choose whether to include or exclude EM structure de-embedding network data in the simulation data set. By default, the de-embedding network data is excluded, which can result in significant savings in the simulation data set size. Reduced data sets save hard disk space and improve data transfer performance with remote simulations.
Additional Information:
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Documentation: “Port De-embedding”.
Cadence Analyst™ 3D FEM EM simulator improvements include:
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The Port Solver Basis Set secondary option is removed. The basis set used in the wave port solver is now always increased by one order.
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The choices for AMR Phase 1 (Ports Only) and AMR Phase 2 (Full Solve) Frequency Modifier secondary options are expanded to include Mid/High and Low/Mid/High.
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Improved support for multiple terminal configurations in wave ports, including stability and support for multiple positive terminals.
The AWR Design Environment platform now offers an RF/microwave design creation environment with import and export functionality to provide a pathway to and from Cadence Allegro® PCB design tools and an export pathway to Cadence Virtuoso® Schematic Editor and Cadence Virtuoso® Layout Suite. You can now create and analyze RF/microwave IP in Microwave Office software, with the schematic and layout shared with Allegro/DE-HDL, and Virtuoso software. Interoperability between these software tools facilitates the design and analysis of RF/microwave, analog, and digital design elements together.
The foundation for interoperability is the Unified Library. Unified Libraries are common databases that Microwave Office, Allegro/DE-HDL, and Virtuoso software can read. They contain the technology, component, and design information required to properly analyze, verify, and manufacture a design.
NOTE: This is a limited release feature.
Additional Information:
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Documentation: “AWR Design Environment/Allegro Interoperability”.
Additional Information:
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Documentation: “AWR Design Environment/Virtuoso Interoperability”.
Simulate EM structures from within the AWR Design Environment platform using the Cadence Clarity™ 3D Solver, a 3D full-wave electromagnetic (EM) simulation software tool. Clarity has the ability to solve much larger problems such as entire modules and complete BAW/SAW filters with greater speed.
NOTE: This is a limited release feature.
Additional Information:
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Documentation: “Clarity 3D Solver”.
Run thermal analysis from within the AWR Design Environment platform using the The Cadence Celsius™ Thermal Solver. You can create Celsius EM structures by either drawing the geometry in the EM editor, or by using EM extraction. After simulating, open the structure in the Celsius original editor to view 3D field plots of the thermal temperature distribution. Temperature results of the Celsius simulation are returned to the AWR Design Environment platform.
NOTE: This is a limited release feature.
Additional Information:
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Documentation: “Celsius Thermal Solver”.
Microwave Office V16 software includes the following minor new features, enhancements, and user interface changes.
The following new circuit models are included in Microwave Office v16 software.
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“Coplanar Waveguide Interdigital Capacitor (Aggregate): CPWICAP”
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“Rectangular CPW Inductor with AirBridge/Underpass (EM Quasi-Static): CPWRINDB”
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“2 Asymmetric Coupled Coplanar Lines on Multilayer Substrate (EM Quasi-Static): GCPW2LNA”
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“2 Asymmetric Broadside Coupled Coplanar Lines on Multilayer Substrate (EM Quasi-Static): GCPWBCGG”
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“Coplanar Asymmetric Line on Multilayer Substrate (EM Quasi-Static): GCPWALIN”
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“Microstrip Interdigital Capacitor on Multilayer Substrate (Aggregate): MMICAP”
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“Tapered Microstrip Line on Multilayer Substrate (EM Quasi-Static): MMTAPER”
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“Tapered Microstrip Line Synthesized to Match (Klopfenstein, Exponential, Triangular): MTAPER2”
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“Microstrip Radial Stub Series on Multilayer Substrate (EM Quasi-Static): MMRSTUB”
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“Microstrip Radial Stub Shunt on Multilayer Substrate (EM Quasi-Static): MMSRSTUB”
The following new circuit measurements/annotations are included in Microwave Office V16 software.
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API access is added to the DesignRuleChecker.ErrorWindow.Title which enables customization of the Error Window title.
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The symbols drawn for single-point optimization/yield goals on graphs now make it clear what type of goal is represented.
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Graphs with measurements using All Sources as the data source now correctly update to include newly added data sources when XML Library elements based upon Touchstone and MDIF data files are brought in to a project.
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The Job Scheduler now starts asynchronously when the AWR Design Environment platform starts, allowing faster initial simulations and enabling the Job Monitor to fetch data sets without requiring an initial simulation.
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Saving changes to a remote host in the Job Scheduler Admin tool now causes the host connection to reset and reconnect with the new parameters so that restarting the running Job Scheduler is no longer necessary to pick up the changes. This improvement applies to both Windows and Linux remote hosts.
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Fixed a layout performance issue when the Layout Editor Mode option Draw route vias as X is selected.
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When setting the Z-position of a subcircuit, the drop-down list now displays the dielectrics in descending order from top to bottom. The dielectric name now displays next to the index to aid in layer selection.
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Implemented the Draw border on window option in the Properties dialog box for Window-in-window views in Output Equations documents.
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When pushing into a SUBCKT using the command, you can now choose which Switch View document to push into when available.
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Added AC analysis support for several ports, including PORT_PS1. For PORT_PS2, an AC source is only added to the 1st tone.
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Noise is now simulated whenever there is an active NPORTF output file measurement for a 2-port and the Write Noise for Active Source parameter is selected.
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You can now Shift- double-click on a schematic node in the Project Browser to open the Layout View of the schematic.
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Increased the column width of the # column in the Simulation window so that job numbers greater than two digits properly display.
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Rich text boxes now support fill translucency.
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Pressing the Shift key while dragging and dropping a file (such as a schematic, netlist, or data file) from Windows Explorer into the AWR Design Environment platform will link the file instead of embedding it.
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Updated the drag and drop mechanism to accept all the files that can be linked to, including Global Definitions and circuit symbol files.
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Dialog boxes that support column filtering, such as the Open Example Project dialog box, now have filtering functionality by default.