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Nonlinear Amplifier, Envelope Co-simulation: NL_S_ENV



NL_S_ENV models a Cadence® AWR® Microwave Office® software nonlinear circuit within Cadence® AWR® Visual System Simulator™ (VSS) communications and radar systems design software using an envelope co-simulation.

The AWR Microwave Office schematic must contain two or more PORTs.

NL_S_ENV does NOT support RF Budget Analysis or RF Inspector simulations. Attempting to run either simulation with an NL_S_ENV block generates an error.


Name Data Type Description Unit Type Default
ID N Element ID   S1
NET S AWR Microwave Office subcircuit name   A
*SIMTYP_TD   Time domain envelope simulator   APLAC Envelope (AP_ENC)
INPORT I Id(s) of the signal input PORT model(s) in the AWR Microwave Office circuit Scalar {1}
DCINPORT I Id(s) of the DC/bias input PORT model(s) in the AWR Microwave Office circuit Scalar  
OUTPORT I Id(s) of the signal output PORT model(s) in the AWR Microwave Office circuit Scalar {2}
DCPOUT E Output source DC power N/A No
FCOUTSPEC S Specification of output center frequencies, in the form mf1+nf2 Scalar f1
FCINSPEC S Specification of input center frequency multipliers, in the form mf1,nf2 Scalar  
*DCPOUTCUTOFF R Cutoff frequency for source DC power output GHz  
*STATUSDLG E Show Status dialog box when processing samples N/A Auto
*SECSPASS I Maximum seconds per simulation pass Scalar 5
*FLTRORDR I Co-simulator baseband filter order Scalar 15
*DIAGDSP E Diagnostics to display N/A None
*IVARTYP   Treatment of parameters for schematic swept variables   Allow any value for numeric, pin to nearest

* indicates a secondary parameter

Parameter Details

NET. The name of the schematic, normally enclosed in quotation marks.

SIMTYP_TD. For more information on this parameter, contact the Cadence Support website for information regarding the use of the Cadence® AWR® APLAC® Transient simulator.

INPORT, OUTPORT. The port indices (the value of the P parameter of the PORT block; indices start from 1) of the PORT models in the schematic to be used for the input and output signals, respectively. You can specify multiple input and/or output ports using a array, as in '{1,2}'.

The input ports must be Source PORT blocks in the schematic, while the output ports must be Termination PORT blocks in the schematic.

DCINPORT. Optional ports for DC bias inputs. Note that samples input to this port are treated as source voltages, and are not considered loaded by the impedance seen looking into the upstream output port.

DCPOUT. Enables/disables the output of the DC source power as computed by the envelope co-simulation. If "Yes", a secondary real-signaled output port is added to the block.

The samples output are power in Watts, and can be used for the DC Power input of the Power Added Efficiency, Time Domain measurement PAE_TD.

FCOUTSPEC. Used to define the center frequencies for the signal output ports. The value must have the form 'mF1 + nF2' where 'm' and 'n' are integers greater than 0 and 'F1' and 'F2' are the center frequencies of input ports 1 and 2 scaled according to FCINSPEC. Each output port typically has its own entry, the entries are separated by ','. Some examples of valid FCOUTSPEC values are:

    FCOUTSPEC = 3f1
    FCOUTSPEC = 2f1+f2
    FCOUTSPEC = 3f1, 2f1+f2

FCINSPEC. Used to scale down the input port center frequencies prior to their use in FCOUTSPEC. The value must have the form 'mF1' where 'm' is an integer greater than 0 and 'F1' represents the scaled input center frequency value for input port 1. If there are multiple input ports, scalings for the other input ports should be separated by ','. If left empty, or an entry not specified for a particular input port, no scaling is applied to that input port's center frequency.

This parameter is typically used to support frequency dividers or other circuits where the desired output center frequency is not a integral multiple of the input center frequencies. For example, a two port 1/2 frequency divider circuit would conceivably use the following values for FCOUTSPEC and FCINSPEC:

    FCOUTSPEC = f1
    FCINSPEC = 2f1

The FCINSPEC in the above example indicates that 'f1' should be 1/2 the center frequency of input port 1. The FCOUTSPEC indicates that the center frequency of the output port should be 'f1', and is therefore 1/2 the center frequency of input port 1.

STATUSDLG. Determines whether to display the Status dialog box when the main simulation is running. If "Auto", the Status dialog box displays if it is taking longer than approximately SECSPASS seconds to process each group of samples. Displaying the Status dialog box provides feedback as to how many samples have been processed, and allows you to cancel the simulation while a block of samples is being processed.

SECSPASS. An approximate maximum number of seconds to allow for processing a block of samples before doing tasks such as updating graphs or allowing interaction with the Cadence® AWR Design Environment® platform user interface.

NOTE: Specifying a large value for SECSPASS and setting STATUSDLG to "No" may make the software unresponsive during a simulation, as both graph updates and user interface actions such as menu selections occur infrequently.

Data Input

Node No. Type Purpose
1 Real/Complex Input Signal

Data Output

Node No. Type Purpose
2 Real/Complex Output Signal

Implementation Details

Unlike the Nonlinear Behavioral Model, (Simulation-based) block (NL_S), NL_S_ENV does not create a behavioral model from the circuit simulation results. NL_S_ENV instead passes samples it receives to, and reads output samples from, the circuit simulator as the input samples are received.

For complex circuits, NL_S_ENV typically processes samples at a much slower rate than the behavioral model blocks, however, its output generally more closely matches the true output. This is particularly true when the signal is compressed or the circuit is highly nonlinear.

Recommendations for Use

Controlling Bias Voltage

The bias voltages of the circuit may be controlled from the VSS simulation. You should set up the schematic with PORT elements at the bias voltage control points. Set the DCINPORT parameter to the port indices of the bias ports, using braces to enter more than one port, such as '{3, 4}'. The ports appear as real-data typed secondary input ports.

The samples received at these ports are treated as voltage source values and are not loaded. For example, if the input to the bias port is a constant value of 10.0, the circuit behaves as if it has a 10.0 V DC voltage source at the corresponding port in the circuit.

Measuring Power Added Efficiency (PAE)

You can measure PAE using the Power Added Efficiency, Time Domain measurement (PAE_TD). You should configure the NL_S_ENV block to output the DC source power by setting the DCPOUT parameter to "Yes". A real-data typed secondary output port is added to the NL_S_ENV block. The output of this port is the DC source power estimate in Watts.

You can use either a Vector Signal Analyzer block (VSA) or a Vector Network Analyzer block (VNA) to measure the input power and the output power of the NL_S_ENV block. Add a Test Point (TP) to the DC source power output of the NL_S_ENV block.

Signal Delay, Gain and Phase Compensation

Because NL_S_ENV must perform internal filtering, it introduces a frequency-dependent signal delay. The circuit itself most likely also introduces a signal delay. NL_S_ENV estimates the signal delay over a bandwidth the size of the data rate, which is the sampling frequency divided by the oversampling rate. It then propagates this value to downstream blocks and measurements to assist in their compensation of signal delay.

When demodulating a modulated signal using a receiver block, or when measuring Error Vector Magnitude (EVM), it is generally best to use an Align Signal block (ALIGN) prior to the receiver or the VSA used to measure the signal. The ALIGN block performs a correlation between the DUT signal and a reference signal to perform delay, gain, and phase compensation.

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