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Chapter 4. Linear Analysis

Cadence® AWR® Microwave Office® software supports linear analysis using the nodal admittance matrix method.

The type of simulator used to analyze a circuit depends on the types of elements and sources present in the circuit along with the type of measurements requested. If all of the elements in a circuit are linear, only the linear simulator runs when you choose Simulate > Analyze. If the circuit contains any nonlinear elements or sources but only linear measurements are requested, then the harmonic balance simulator solves for the DC operating point. The circuit is linearized about this operating point and analyzed by the linear simulator.

4.1. Using the Linear Simulator

The AWR Microwave Office linear simulator is built using object-oriented techniques that enable fast and efficient simulations of linear circuits. One of its trademarks is a real-time tuner that allows you to see resulting simulations as you tune. It also allows you to perform optimization and yield analysis.

The linear simulator is used to analyze circuits that are a function of frequency, but are independent of drive level, such as low noise amplifiers, filters, couplers, and dividers. Examples of linear elements are capacitors, inductors, resistors, microstrip, stripline and coaxial transmission lines. Some of the measurements associated with linear circuit analysis are gain, stability, noise figure, reflection coefficient, noise circles, and gain circles.

4.1.1. Linear Solver

The AWR Microwave Office linear simulator uses the nodal admittance matrix method. This method computes the response of the linear network from an admittance matrix equivalent of the N port network. The N port network can include element models like microstrip, S-parameter files, or imported netlists that represent text-based versions of a schematic.

4.1.2. Linear Circuit Design

Linear circuit design in the AWR Microwave Office program is easy and intuitive. The process to create a linear design begins with placing linear elements in a schematic, then adding ports and sources to define the network. The elements can be data files, models, or netlists. The network then registers as a subcircuit in the Elements Browser and can be used in other schematics. Circuit hierarchy can be used for very complex designs by placing subcircuits within a top level schematic. After the schematic is complete, graphs and measurements are defined to view the simulated data. All of the popular measurements like scattering parameters, stability factor, and maximum available gain are included with the program. If necessary, you can activate element parameters for tuning, and use a real time tuner to view changes in the response instantaneously. Optimization and yield analysis are also available to further refine the design.

4.1.3. Linear Noise Analysis

AWR Microwave Office software simulates linear noise using noise correlation matrices. Noise contributions from the following are accounted for in the simulation:

  • Thermal, shot, and flicker as defined by nonlinear device models. Noise from NL models is generally bias and temperature-dependent. For linear noise analysis, these noise sources are linearized about the operating point.

  • Thermal noise from lossy, passive elements. This noise is scaled by T/T0 where T0 is defined by convention to be 290K. T is controlled by the variable _TEMPK and defaults to 290K. _TEMPK can be overridden by placing an equation that redefines _TEMPK to another value. Note that this value must always be in degrees Kelvin.

  • Noise from active two-port devices as defined by the noise parameters Fmin, Gamma Opt., and Rn in an S-parameter data file.

  • Any noise source elements, both linear and nonlinear, present on the schematic.

4.1.4. APLAC Linear Subcircuit Caching

Subcircuit caching can reduce the simulation time in designs that contain linear portions that do not change very often, but are expensive to compute. The Cadence® AWR Design Environment® platform uses subcircuit hierarchy when searching for cache candidates. When a linear portion of a circuit is accepted for caching, AWR Design Environment software stores its Y-parameters and noise parameters on disc. When the same subcircuit is next simulated, the Y-parameter data is read from the disc cache.

Subcircuit caching can speed up the simulation when:

  • there are multiple instances of the same subcircuit in the same top level simulation

  • there are multiple top-level simulations in the same project using the same schematic as a subcircuit

  • re-opening a project that has previously stored subcircuit cache data

Subcircuit caching is used for the Cadence® AWR® APLAC® Linear simulator only. To enable this option, on the Circuit Options dialog box APLAC Sim tab, display the secondary options, and under APLAC Simulator Options/AC Options, select Subcircuit caching. When enabled, all subcircuits are examined for caching candidates. The automatic detection tries to identify subcircuits with large potential speed-up, typically subcircuits with a large number of internal nodes compared to the number of ports. Nonlinear subcircuits are also candidates, but only the linear portion of the subcircuit can be cached.

You can override this automatic selection by placing SUBCKT_CACHE control blocks in the subcircuit schematics that are not often modified. If there are any SUBCKT_CACHE blocks in the circuit, the automatic selection is disabled and only the subcircuits containing the control blocks are considered for reading or writing the cache. Note that a subcircuit containing a SUBCKT_CACHE block may still be discarded from caching.

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