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Microwave Office Layout Guide

NI AWR Design Environment v14.04 Edition

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For patents covering NI AWR software products/technology, refer to ni.com/patents.

The information in this guide is believed to be accurate. However, no responsibility or liability is assumed by National Instruments for its use.

Table of Contents

1. Preface
1.1. About This Book
1.1.1. Additional Documentation
1.1.2. Typographical Conventions
1.2. Getting Online Help
2. Layout Overview
2.1. The Layout as Another View of the Schematic Database
2.2. Layout Objects (Cells)
2.2.1. Built-in Parameterized Cells
2.2.2. Artwork Cells
2.2.3. User-Defined Cells
2.2.4. No Layout (Ports, for Example)
2.3. Layout Fundamentals
3. Layout Editing
3.1. Schematic and Schematic Layout Interaction
3.1.1. Element Symbol Color
3.1.2. Initial Layout Shape Placement
3.1.3. Snapping Layout Cells
3.1.4. Freezing and Anchoring Shapes
3.1.5. Layout Placement Commands
3.1.6. Cross-selecting in Views
3.2. Layout Manager
3.2.1. Drawing Layer Pane
Hiding Non-active Layers
Selecting a Configuration
Editing Drawing Layers
3.2.2. Artwork Cell Libraries
3.2.3. Navigating the Libraries in the Layout Manager
3.3. Layout Editing
3.3.1. Schematic Layout/EM Layout Editor
3.3.2. Artwork Cell Editor
3.4. Schematic/EM Layout Draw Tools
3.4.1. Draw Tools Toolbar
Ellipse (Ctrl+E)
Path (Ctrl+L)
Polygon (Ctrl+P)
Rectangle (Ctrl+B)
Text (Ctrl+T)
3D Clip Area
Drill Hole
3.4.2. Layout Shapes Editing
Grid Snap (Ctrl+G)
Orthogonal (Ctrl+O)
Shape Selection
Multiple Selection
Multiple Selection Editing
Move with Reference
Copy with Reference
Command Repeat Mode
Gravity Points
Rotation and Flipping
Restricted Object Selection
3.4.3. Polygon Editing
Adding Polygons
Editing Points and Edges
Deleting Shape Vertices
Stretching Shape Vertices
Adding Shape Vertices
Filleting or Chamfering Vertices
Removing Fillets or Chamfers
Adding/Editing Cutouts and Arcs
Adding Cutouts
Editing Cutouts
Adding Cutlines
Editing Arc Segments
Array Copy
Area Stretching (Stretch Area)
Slicing Polygons (Slice Shape)
Creating Notches (Notch Shape)
Merge Shapes
Fracturing Polygons (Fracture Shapes)
Shape Mirroring (Mirror)
Shape Modification Operations
3.4.4. Coordinate Entry
3.4.5. Measuring Tools
Standard Ruler
Layout Ruler
Dimension Line
3.4.6. Zooming and Panning
View All
View Area
Zoom Previous
Zoom In
Zoom Out
3.4.7. Grouping
3.4.8. Alignment Tools
3.5. Intelligent Cells (iCells)
3.5.1. Standard iCells
3.5.2. User-Defined iCells
3.5.3. Generalized iCells
3.6. TRACE Elements
3.6.1. TRACE Editing
Adding a Bend
Moving Bend Position with Overall Length Constant
Moving the Bend Position and Changing the Overall Length
Adding a Bend After Initial Bend
Rotating a Segment
3.6.2. TRACE Routing
Maintaining the Line Length
3.6.3. Snap to Fit
3.6.4. Symmetric Circuits
3.7. Electrical Net (iNet) Elements
3.7.1. Defining iNets
Defining iNets in a Schematic
Defining iNets in a Layout
3.7.2. Preparing to Route
Default Vias and Discontinuities
Minimal 2 iNet Route Via Mode
Default Widths and Line Types
3.7.3. Starting Routes
3.7.4. Entering Routes
iNet Status
Connecting to Non-orthogonal Faces and Area Pin Sides
Coordinate Entry
3.7.5. Editing Routes
End Points
Line Types
Shape Properties
Bend Styles
Reroute Mode
Snap to Fit
Reshaping Routes
Snap Cell Connections
3.7.6. Selecting iNets in Layout
3.7.7. Deleting an iNet
3.7.8. Associating and Disassociating iNets
3.7.9. iNet Cleanup
Invoking the Command
Merging End-Connected Routes
Inserting Crossovers
Inserting Crossovers Incrementally
3.7.10. Copying iNets
3.7.11. Simulating with iNets
3.7.12. Additional iNet Commands and Options
Net Highlight
Selecting All iNets
Repeat Command
Colinear Points
Verifying Connectivity
Current Density
RC Equivalent
3.8. Routes
3.8.1. Adding Routes
3.8.2. Adding Vias
3.8.3. Preparing To Route
3.9. Placement Mirroring
3.10. Shape/Layer Modifiers
3.10.1. Adding Modifiers
Edge Modifier
Point Stretch Modifier
Width Modifier
Radius Modifier
Ellipse Size Modifier
Array Modifier
Spacing Modifier
Polar Spacing Modifier
Stretch Area Modifier
Control Point Modifier
Layer Offset Modifier
Layer Resize Modifier
Layer Boolean Modifier
Layer Corner Modifier
Shape Preprocessor (SPP) Modifier
3.10.2. Layout Modifier Order
3.10.3. Editing Modifiers
3.10.4. Debugging Modifiers
3.11. Via Fill and Via Fence
3.11.1. Setting Up the Via Fill/Fence Operation
3.11.2. Via Fill
Running the Via Fill Operation
Via Fill Presets
3.11.3. Via Fence
Running the Via Fence Operation
Via Fence Presets
3.12. Artwork Cells
3.12.1. Editing Artwork Cells
Creating an Area Pin
3.12.2. Stretching Artwork Cells
3.12.3. Saving Artwork Cells
3.12.4. Flattening Parameterized Layout Cells
3.12.5. Creating Artwork Cell Libraries
3.12.6. Saving Artwork Cell Libraries
3.12.7. Loading Artwork Cell Libraries
3.12.8. Assigning Artwork Cells to Layout of Schematic Elements
3.13. Layout Cell Properties
3.13.1. Cell Options
Line Type
Line Type Definitions
Layer Mapping
Flip Cell
Orientation Angle
Freeze Position
Use For Anchor
Stretch to Fit
3.13.2. Face Properties
Face and Snap to
Snap To Adjacent
Multi-layer Drawing
Face Justification
3.13.3. Local Cell Parameters
4. Layout Configuration
4.1. Setting Layout Options
4.1.1. Orthogonal vs Non-Orthogonal Design Styles
4.1.2. Grid Options
4.1.3. Layout Cell Snap Options
4.1.4. Preventing Layout Problems
Subcircuits and Artwork Cells Must be Orthogonal
pCell Rounding
Path Vertices on Grid
Different Length Faces
Artwork Cells with Odd Multiples of the Grid
Snapping vs Dragging
4.1.5. Diagnosing Layout Problems
4.2. Configuring Layout Mode Properties
4.3. Drawing Layers and Model Layer Mapping
4.3.1. Layer Mapping of Layout Cells
4.3.2. Model Layer Conventions
4.3.3. Creating the Layer Mapping
GDSII Layer Mapping
GDSII Layer Conventions
GDSII Layout Cells
Importing GDSII Libraries
4.4. The Layout Process File (LPF)
Default Units
Default Values
Drawing Resolution Settings
Line Type Definitions
Process Development Kit Line Types List
Structure Type Definitions
Capacitor Definitions
PAD Definitions
Via Definitions
pCell Multi-layer Line Drawing
Airbridge Drawing Object Selection
DRC Rules File
Connectivity Rules
Default Layout Font
4.4.2. The $LAYER_SETUP_BEGIN/END Section
Drawing Layers Properties
Layer Mapping Properties
EM Layer Mapping Properties
User Defined Drawing Layer Fill Patterns
4.4.3. The $EM_SETUP_BEGIN/END Section
Default EM Enclosure Size
Default EM Layers
EM Conductors
5. Layout Verification and Export
5.1. Design Rule Checking (DRC)
5.1.1. Running Design Rule Check
Cell-Based Checking
Rat Lines Checking
Polygon-Based Checking
Polygon-Based Rules File
Area DRC Check
5.1.2. Working with DRC Errors
Identifying DRC Errors
Customized DRC Error Messages
Checked Errors and False Errors
Save DRC Errors
Load DRC Errors
Copy DRC Errors
View All Errors
View Rule Error
Next Rule Error
Previous Rule Error
Next Error
Previous Error
5.1.3. GDSII Compare
5.2. LVS (Layout vs Schematic)
5.2.1. Preparing an RF Schematic for LVS
5.3. Connectivity Checking
5.3.1. Running the Connectivity Checker
Defining a Short
Artwork Cells, pCells, and EM Subcircuits
Ground Connections
Unsupported Connectivity Checker Items
5.3.2. Connectivity Highlighting
Highlight Connectivity All
Highlight Connectivity Probe
Highlight Connectivity Rules
Layer Visibility
Using Hotkeys
Using Positive and Negative Layers
Multiple Technology Designs
5.3.3. Connectivity Rules
5.3.4. Connectivity Rules Syntax Errors
No Rules Defined
Syntax Error in Rule Keywords
Drawing Layer Not Defined
5.4. Exporting the Layout
5.4.1. Setting Up Export File Mapping
5.4.2. Exporting Unioned Polygons
5.4.3. Exporting Subcircuits as Instances
Artwork Instance Export Options
Layout Cell Export Options
5.4.4. Negative Layers
5.4.5. Exporting Coplanar Waveguide Layouts
5.4.6. Reticle Creation

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