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Chapter 16. MMIC: Supplemental Topics

This section provides additional MMIC design related information.

NOTE: The Quick Reference document lists keyboard shortcuts, mouse operations, and tips and tricks to optimize your use of the NI AWR Design Environment suite. Choose Help > Quick Reference to access this document.

Navigating Design Hierarchy: Schematic and Layout

There are several useful concepts to understand when working with hierarchical designs.

You have different options for accessing schematics at various levels of hierarchy, including:

  • In the Project Browser you can view a design's hierarchy and double-click on any schematic node to open that schematic in a separate window. For example, the "Distributed Design" schematic has three subcircuits.

  • You can open a subcircuit in its own window by selecting it in the schematic, right-clicking, and choosing View Referenced Doc.

  • You can push down into a subcircuit from the current schematic and a new window opens. Select the subcircuit, right-click, and choose Edit Subcircuit, or click the Edit Subcircuit button on the toolbar. The subcircuit replaces the schematic in the schematic window.

  • To go back up one level, with nothing selected, right-click in the schematic and choose Exit Subcircuit, or click the Exit Subcircuit button on the toolbar.

For schematic annotations, there is an important difference when pushing into a subcircuit versus opening the subcircuit in a new window. Schematic annotations are simulation results that display directly on the schematic, such as DC bias values. (NOTE: To add a schematic annotation to a schematic, right-click the schematic in the Project Browser and choose Add Annotation, then select an annotation.) To view the top level schematic annotation in a lower level, you use the Edit Subcircuit command. In this mode, the subcircuit knows which top level schematic is referencing it and can display the annotations.

For example, the following figure shows the "Lumped Element Design" schematic after simulation. Notice that the DC currents display on the schematic.

If you open a new window for "lumped_output_match", the schematic does not display the annotation, as shown on the left in the following figure. If you push into the subcircuit, the schematic does display the annotation, as shown on the right of the figure.

Note also that the schematic title bar shows which mode is used. In a new window, the title bar displays only the schematic name.

When pushing into the schematic, the title bar shows the hierarchy path.

You have similar options for accessing schematic layouts at various levels of hierarchy, including:

  • In the Project Browser you can view a design's hierarchy and you can right-click on a schematic and choose View Layout to open that schematic layout in a separate window.

  • You can open a subcircuit layout in its own window by double-clicking the subcircuit in the layout.

  • You can push down into a subcircuit layout from the current schematic layout, allowing you to edit the subcircuit while still viewing the entire layout. Select the subcircuit, right-click, and choose Edit in Place or click the Edit in Place button on the toolbar.

  • To go back up one level, with nothing selected, right-click in the schematic layout and choose Ascend In Place Edit, or click the Ascend in Place Edit button on the toolbar.

The following "Distributed Design" schematic layout shows an example of "edit in place".

When you select the "distributed_input_match" subcircuit on the left, right-click it and choose Edit in Place, the layout displays as follows.

The layout for the subcircuit displays in normal colors. You can edit those shapes in context from the rest of the layout, which is dimmed and not editable.

NOTE: You can use layout modes to change how subcircuit layouts display in the top level layout. Choose Layout > Layout Mode Properties to display the Layout Editor Mode Settings dialog box. The outlined options in the following figure apply to hierarchical layout viewing.

Cross-selecting Between Schematic and Layout

When working on a design, you may want to access the electrical element properties from the layout, or the layout properties from the schematic. When you select an item in the schematic, that item is highlighted in the layout, as shown in the following figure.

Similarly, when you select an item in the layout, that item is shown with a cross in the schematic, as shown in the following figure.

These displays are only visuals of what is selected. To access properties you use different commands. In a layout, you can select the item, right-click and choose Element Properties to display the Element Options dialog box. You can also open this dialog box by double-clicking an element in the schematic.

Accessing layout options from a schematic is not as simple. There are various licensing configurations that enable circuit design, but not all of them have layout enabled. Every Microwave Office license has a schematic, but not all have layout capability, so the layout options are not available from the schematic. To access layout options from a schematic:

  1. Select the item in the schematic.

  2. Right-click and choose Select in Layout.

  3. Choose View > View Selected to zoom in on the selected element.

  4. Right-click the selected shape and choose Shape Properties to display the shape properties.

There is an additional command for placing an element selected in a schematic into the layout:

  1. Select the item in the schematic.

  2. Right-click and choose Place in Layout.

  3. The layout opens if not already opened, and the layout for that item is selected so you can move the cursor and click to place the item in the desired location.

Using Intelligent Parameter Syntax

Intelligent Parameter Syntax is a way to have models get their parameter values from other models' parameters. This syntax gives you more flexibility and ease of use than using variables to tie two or more parameters to the same value. There are two variations of this syntax.

The first intelligent syntax format is setting an element parameter value to be equal to the parameter of a specific model parameter connected to a specific node of the current model. The simplest form of this syntax is used with intelligent discontinuity models (whose names end with a $ symbol) where the models are already set up to use this syntax. The syntax used is "P@N", which specifies to look at the model connected at node "N" of this model and use the parameter "P". For example, the following is the parameter listing for the MTEE$ model (after you press the Show Secondary button.

Each of the model parameters is getting the W parameter from the model connected at the node listed. This works most of the time because lines should always be connected to discontinuity models. In some cases, this model produces an error if there is no W parameter for the model connected at a specific node. This typically happens if the model has some other width parameter, such as W1 or W2, and is easy to fix by correcting the width parameter. In the previous example, if an M2CLIN port 1 is attached at port2 of the MTEE$, the model parameters appear as follows.

The second intelligent syntax format is used to assign one parameter to use the same value as another parameter. The syntax is "P@EL.ID", where "P" is the parameter name, "EL" is the element name and "ID" is the ID of that element. This syntax is commonly used to get one model to match another, typically called master-slave syntax. Additionally, it is common for TRACE elements to use this syntax to be able to edit the shape of the master, while the slave follows automatically to build a system that is always symmetric. An example is a Wilkinson power divider. The following schematic shows an example of MTRACE2 elements connected to the source of a FET. In this design is it critical that each path is identical.

Notice how TL2 is the master and TL1 is the slave. The following shows the model parameters including the secondary parameters for the slave.

(NOTE: Intelligent syntax cannot be used for any substrate definition parameter. The MSUB parameter in this case is using a globally defined substrate definition. See “Intelligent Cells (iCells)” for details.

Layout: Using Automatic Interconnect

Automatic interconnect (also called "Bridge Code") is part of an NI AWR PDK that changes how lines draw when connected to other components (for example, capacitors and transistors). While the automatic interconnect is very powerful for ensuring your layout is DRC correct, there are issues to consider when creating your design.

Using More Than Two Connections at a Node

There are several scenarios in which you connect more than two elements to a node during MMIC design, for example:

  • Using a 3-node transistor model where vias need to be placed on either side of the transistor, as shown in the following figure.

  • Using a bias line where the bias flows over one of the plates of the capacitor, as shown in the following sample schematic.

    The 3D layout shows that the via is connected to the bottom of the cap and the two lines are properly connected to the top layer of the cap.

The automatic interconnect does its best to determine how to draw the proper connections; however, this is an ambiguous situation. The line is connected to both another line and a capacitor, so it must determine which connection to use to draw its automatic interconnect. There are rules that prioritize certain component types.

In these situations, NI AWR strongly recommends that you configure the layout to specify which layout connection to make. There are layout specific settings to force faces for individual elements to connect properly. An added benefit of configuring these faces is that the settings also determine the proper face to use when snapping. This is demonstrated with the previous capacitor example.

To configure face connections:

  1. Select a shape in layout, right-click and choose Shape Properties to display the Cell Options dialog box. In this example, you select the lower line in the layout.

  2. Click the Faces tab.

  3. Position the dialog box on the screen so you can view it next to the schematic layout in which you are working.

  4. Select the proper Face. You can determine which face is correct by viewing the layout; the selected face draws in blue. The following figure shows the dialog box and layout with face 2 selected.

  5. In Snap to, select the appropriate face to snap to. You can determine which face is correct by viewing the layout; the selected face draws in red. In this example there are five possible Snap to locations because there is one other line and one capacitor connected to that node.

    The capacitor has four possible connection locations: one on each side of the capacitor. In this example, you try the capacitor connections until you find the correct one, where the red line matches up with the blue line.

The same steps are repeated for the other line connected at this node. When complete, the automatic interconnect is guaranteed to draw correctly and the layout snapping uses the requested faces.

Working Through Hierarchy

Automatic interconnect can work through hierarchy, but there are limitations. Automatic interconnect can look down through a hierarchy, but not up. If an element is connected to a subcircuit, that element can change its drawing. However, an element down in a subcircuit cannot change its layout based on what is connected at a higher level. The subcircuit can be used in many places, so the automatic interconnect may be different for each instance of the subcircuit.

The following example of plated lines connected to either side of a capacitor illustrates this issue. The automatic interconnect changes the line drawing on each side of the capacitor to make the proper connections. The following figure shows a 3D view of proper connections.

The first possibility is to put the capacitor in a lower level of hierarchy.

and then connect the lines at a higher level.

The following figure shows the 3D layout with the Connectivity Highlighter on, where each connected shape displays in a different color.

The second possibility is to put the lines in a lower level of hierarchy

and then connect the capacitor at a higher level.

The following figure shows the 3D layout with the Connectivity Highlighter on. The capacitor is now shorted out due to improper automatic interconnect.

Artwork Cells and EM Structures

When using artwork cells as layout cells for elements, or using EM subcircuits as building blocks, you can configure how automatic interconnect works when connecting lines to these elements. For artwork cells, you create cell ports that define the connectivity locations. For EM structures, you add ports for simulation purposes. For both cell ports and EM ports, select the port, right-click and choose Shape Properties to display the Properties dialog box and then click on the Cell Port or Cell Pin tabs. In the NI AWR Design Environment Dialog Box Reference, see “Properties Dialog Box: Cell Pin Tab ” for details on this dialog box.

The correct setting may not be obvious because you cannot easily determine the connect type for the built-in parametrized cells in a PDK. To determine the connect types for a given cell:

  1. Place an element using the parametrized cell in which you are interested.

  2. Select the element in the layout.

  3. Choose Layout > Make GDSII Cell to display the Make New GDS Cell dialog box.

  4. Specify a Library name and Cell name and click OK to open an artwork cell window with cell ports added for each face location.

  5. Select the desired face, right-click, and choose Shape Properties to display the Properties dialog box.

  6. Click the Cell Port tab to view the Connection Type the face uses.

Discontinuities Without Lines

In microwave design, discontinuity models should not be connected directly to one another. Electrically, these discontinuities produce evanescent modes that decay some distance from the discontinuity. The models account for these modes only if there is enough line connected to these discontinuities-- typically two substrate thicknesses.

In addition, the automatic interconnect does not function properly when there are discontinuities hooked together. The following figures demonstrates this issue.

The following is the layout for this schematic.

Notice that all of the proper line offsets are drawing correctly in the area where the line connects to the bend at the top.

If you remove the line, the schematic displays as follows.

The following is the layout for this schematic.

Notice the area where the line connects to the bend at the top. The layer offset from the MTEE model is pushing outside of the layers for the MBEND, which might cause DRC errors.

Besides the layout being incorrect, the electrical results using these circuit models is wrong because there is no line between the discontinuities. If you must simulate this geometry, EM simulators such as AXIEM or Analyst can properly model them.

Layout: Changing Background Color

By default, the layout background color is white with black grid markers. You may prefer a black background, as the fill patterns for some PDKs may be optimized for a black background. The simplest way to switch background colors is to choose Scripts > Layout > Toggle_Background_Color to toggle both the background and grid colors. If you want to manually change these colors, choose Options > Environment Options to display the Environment Options dialog box, click the Colors tab and then select the desired display colors.

Layout: Snapping Strategy

The NI AWR Design Environment software has two very different layout snapping modes. You can access these modes on the Layout Options dialog box Layout tab in the Snap together option (choose Options > Layout Options). Auto snap on parameter changes snaps the objects for that layout whenever you change a parameter, or through tuning or optimization. The manual snap settings (Manual snap for selected objects only and Manual snap for all objects) only snap together when you use the snap commands for the entire layout or for only the selected object.

If you use Manual snap for selected objects only at the beginning of the design, you can complete the initial placement of layouts without encountering errors in the layout every time a parameter changes. After the initial placement of elements you can switch to Auto snap on parameter changes. With this approach, as you change parameters, tune, or optimize, the layout stays connected.

NOTE: Regardless of the Snap together setting, when using extraction and optimization, the layout always snaps together so the proper shapes can be EM simulated.

Layout: Adding Text

Creating DRC clean text in layout can be problematic. The proper approach depends on how each individual foundry addresses the problem. You should ask your foundry provider what is recommended for adding layout text. There are several possible solutions to the problem, including:

  • A specific text element that creates DRC clean layout. This block is added to a schematic and the text is typed as a parameter of the element and then it draws DRC clean in the layout.

  • Included with the PDK is a GDSII library that has each individual letter and number drawn as a cell. You can use these cells in your schematic layout to create your text.

  • Some processes do not care about DRC rules in text. NI AWR recommends using “Arial Rounded MT Bold” font. It looks good and is easily read under a microscope when viewing the fabricated MMIC. The following steps explain how to add this text.

To add text objects:

  1. Click in a layout window to make it active.

  2. Click the Layout tab to open the Layout Manager. In the Drawing Layers pane, select the proper layer.

  3. Choose Draw > Text or press Ctrl + T to add a text object.

  4. Click in the layout to place the origin of the text object.

  5. Type your text and press Enter or click outside the text box when done.

To edit existing text:

  1. Select the text object, right-click and choose Shape Properties to display the Properties dialog box.

  2. Click the Layout tab to change the Draw Layers used for the text.

  3. Click the Font tab to change the Font type, the font Height and attributes, and the Draw as polygons setting. This option determines whether the text is drawn as polygon shapes on a given layer (the shapes are included on that layer during fabrication) or if the text remains a text object that is visible on the layout but not on any layer for fabrication.

  4. To edit the text itself, double-click the text to enter edit mode and make changes.

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