This chapter covers topics related to Monolithic Microwave Integrated Circuit (MMIC) design. The Cadence® AWR Design Environment® platform has many unique features to enable efficient and accurate simulation for this type of design. These features allow you to focus on design tasks instead of design task management. Process Design Kits (PDKs) available for the program should have all of the features described here enabled. This guide contains links to other AWR Design Environment platform documents that are online. When reading the print version of this document you can follow links by choosing www.awrcorp.com/download/kb.aspx.to open the guide electronically, or you can find the linked document in the Cadence AWR® Knowledge Base at
The examples in this chapter use a simple MMIC low noise amplifier design to demonstrate MMIC features. MMIC technologies typically have multi-layer lines that differentiate MMIC from other types of high-frequency design. Most MMIC processes have at least two metal layers on top of the substrate used for routing signals. These metal layers can be used as the bottom and top plate of a capacitor, or the dielectric in between can be etched away to form a metal line that has the thickness of both metal layers to reduce loss, handle more current, and increase coupling between structures. The proper manufacturing drawing for these layers typically has small offsets between the layers. For example, in this process, the multi-layer line draws as shown in the following figure.
Metal1 and Metal2 are the same size, and the Dielectric Via is inset 2um from the other layers.
The example used in this chapter is named
MMIC_Getting_Started.emp. To access this file from a list of
Getting Started example projects, choose to
display the Open Example Project dialog box, then
Ctrl-click the Keywords column header and type
getting started mmic" in the text box at the bottom of the
document lists keyboard shortcuts, mouse operations, and tips and tricks to optimize
your use of the AWR Design Environment platform. Choose to
access this document.
The goal of the design is to achieve 1 dB noise figure and greater than 10 dB gain at 10 GHz. The 2D layout of this design is shown in the following figure.
The electrical response of this design is shown in the following figure.
The purpose of this example is to show MMIC-related features, not the design performance of this low noise amplifier. The design technology is a Cadence process created to build example circuits. The parts have realistic values but the circuits cannot be fabricated anywhere.
This design is completed in three stages. The relevant schematics and graphs for each stage are organized under the Project Browser User Folders node. User folders are an optional way to group related window types together for a design. In large designs, it is helpful to organize your graphs, schematics, EM structures and other project items in a folder to easily see which items are related. User folders are used in this example because certain exercises need specific graphs and schematics open, and referencing their user folder simplifies these references.
First, the device is characterized for its noise and gain characteristics. The documents used for this stage of the design are in the "Device_Characterize" user folder. Source feedback is added to move the optimal noise match closer to the ideal input match of the device. The device and its feedback are done in separate schematics for use hierarchically. This allows only one instance of the model in the entire design, reducing the potential for error if changes are made. Additionally, the gate and drain bias voltages are defined with variables in the "Global Definitions" document for the same reason that the device hierarchy is done separately-- so there is one master value for each. Several different topologies of the circuit are built (lumped versus distributed) and hierarchy is not as straightforward as using global variables to keep the bias values consistent through different versions of the design.
Next, the input and output matching networks are designed using lumped elements first. The documents used for this stage of the design are in the "Circuit" user folder. Both matching networks are done in their own schematics and then used hierarchically in the total circuit design. This allows you to easily measure the impedance looking into any port of the matching network. For LNA design, this is necessary to make sure the impedance presented to the device is near the optimal noise match impedance. The design is then converted from lumped elements to distributed elements. These are kept as separate top level schematics for comparison of the lumped and distributed performances.
Finally, the metal for the design is EM-simulated using the extraction flow. The documents used for this stage of the design are in the "Extraction" user folder. An additional level of hierarchy is created so the results with and without EM results are easily compared. In general, adopting a test bench approach to your designs is beneficial. Your designs are completed in one level of schematic hierarchy while all of the different ways to measure results are done one level up in hierarchy, so copies of design pieces are never made.
Hierarchy is typically used in MMIC design to help organize and reduce errors. There are various ways to navigate through hierarchical designs. See “Navigating Design Hierarchy: Schematic and Layout” for details. Additionally, MMIC design generally requires working in both Schematic and Layout Views. It is helpful to know the proper ways to cross-select from one view to the other. See “Cross-selecting Between Schematic and Layout” for details.