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Chapter 15. MMIC: Verifying Designs

This chapter shows various ways of verifying whether your design is ready for manufacturing using the MMIC_Getting_Started.emp project opened in the MMIC: Designing MMICs chapter and continued in the MMIC layout and extraction/simulation chapters.

Using the Connectivity Highlighter

The Connectivity Highlighter displays a layout with different colors, one color for all electrically connected metal. This tool is intended for visual inspection of the layout. Note that this example has several levels of hierarchy and the Connectivity Checker runs through all of them. See “Connectivity Highlighting ” for details on the Connectivity Checker. To view this feature:

  1. Open the layout for the "Distributed Design" schematic.

  2. Run the Connectivity Highlighter by choosing Verify > Highlight Connectivity All. The layout displays similar to the following.

    Each electrically connected group of shapes displays in one color. There is a fixed set of colors, so if shapes near each other have similar colors, you can rerun the Verify > Highlight Connectivity All to change the layout connectivity colors. Your colors may differ from those displayed because each time the check is run, the colors displayed are different.

    The connectivity display also applies to the 3D layout view.

  3. Turn off the connectivity display by choosing Verify > Highlight Connectivity Off.

At times, you might only want to highlight the connectivity of parts of your layout. For a MMIC, you may commonly want to highlight all metal that is connected to ground. You can do this with the Connectivity Probe mode. To run this mode, choose Verify > Highlight Connectivity Probe. Click a shape to toggle its connectivity. You are in Connectivity Probe mode until you press the Esc key. For example:

  1. With the "Distributed Design" window active, choose Verify > Highlight Connectivity Probe.

  2. Click on a via to highlight all the grounds in the circuit, as shown in the following figure.

  3. Click over a via again to turn off the highlighting for all the grounds.

  4. Click over the left-most capacitor, and both connected nets for either side of the capacitor display highlighted, as shown in the following figure.

NOTE: If you use these commands often, you should set up hotkeys to run them.

Using the Connectivity Checker

The Connectivity Checker expands on the Connectivity Highlighter by checking the layout connectivity versus the schematic connectivity for differences. (NOTE: The Connectivity Checker assumes that the layout for the device components (for example, transistors, capacitors, and resistors) are correct, so the Connectivity Checker is not a replacement for LVS for final verification). See “Connectivity Checking ” for details on the Connectivity Checker. To use the Connectivity Checker:

  1. Open the layout for the "Distributed_input_match" schematic and select the left-most line in the design connected to the input capacitor.

  2. Right-click and choose Shape Properties to display the Cell Options dialog box, then click the Layout tab and change the Line Type from Metal_2 to Metal_1.

    This change causes a connectivity problem in layout due to the way Bridge Code works through hierarchy. (See “Layout: Using Automatic Interconnect” and “Working Through Hierarchy” for more information on Bridge Code and hierarchy issues). The Connectivity Highlighter in the "Distributed Design" schematic layout displays this problem as follows.

    Visual inspection, however, is not a good strategy for finding connectivity problems in complex designs.

  3. Choose Verify > Run Connectivity Check to compare the layout versus schematic connectivity. When the check is complete, an error window displays.

  4. Click an error to open both the layout and the schematic and highlight where the error is found.

    The different views open as you navigate through the errors.

  5. When you are done viewing errors, choose Verify > Clear LVS Errors.

NOTE: Right-click in the error window and choose Error Marker Options to open the Error Marker Options dialog box to control error display and navigation. See “Error Marker Options Dialog Box ” for more information.

Using Layout Vs Schematic (LVS)

Each foundry develops its own LVS flow, so you should contact the foundry for information on using LVS. Many LVS flows use the error viewer (see “Using the Connectivity Checker” for details). This section shows you how to navigate when using the foundry-supplied LVS flow. See “LVS (Layout vs Schematic) ” for full details on using LVS in the NI AWR Design Environment software.

Design Rule Checking (DRC)

The NI AWR Design Environment software has its own simple DRC engine as well as the capability to run the foundry specified "sign-off" DRC engine. You should contact the foundry for information on using their "sign-off" DRC engine. Many DRC flows use the DRC error viewer used by the NI AWR DRC engine. This section introduces information on how to navigate and find errors, rather than focusing on the specific DRC engine or rules run. See “Design Rule Checking (DRC) ” for details on using DRC in the program. To view an example:

  1. Open the layout for the "Distributed Design" schematic.

  2. Choose Verify > Design Rule Check to display the following window.

    NOTE: If your rules list does not match this figure you need to load the proper rule deck for this example. To locate the folder in which the example PDK is located, choose Help > Show Files/Directories.

    Find “Libraries” in the Name column and double-click it to open the Windows Explorer. Navigate to the …\example_pdks\mesfet\Library\ directory. The DRC rule deck is a file named drc_rules.txt, and you now have the path to the folder it is in.

    Back in the DRC window, click the Load Rules File button and browse to the folder that contains the drc_rules.txt file. Double-click the file and your rules list should now match the list in the previous figure.

  3. Select the rules you want to run and then click the Run DRC button to run the DRC check. When the check is complete, the Design rule violations error window displays.

  4. Double-click an error to magnify it in the Layout View.

  5. Double-click a rule group header.

    The layout zooms to show all of the errors in that group.

  6. Double-click an individual error and the layout zooms to that error. For example, click on the top failure.

    The layout zooms to show the individual error.

  7. You can move each error into a Checked Errors or False Errors category by right-clicking the individual rule and choosing the appropriate option.

NOTE: Right-click in the error window and choose Error Marker Options to open the Error Marker Options dialog box to control error display and navigation. See “Error Marker Options Dialog Box ” for more information.

Completing the MMIC Example

The following chapter includes additional information about MMIC design related topics. NI AWR highly recommends that you review this material to further your understanding of MMIC design in the NI AWR Design Environment software.

Please send email to awr.support@ni.com if you would like to provide feedback on this article. Please make sure to include the article link in the email.

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