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Chapter 13. MMIC: Layout Features

This chapter describes several powerful layout features for MMIC design using the MMIC_Getting_Started.emp project opened in the MMIC: Designing MMICs chapter.

Specifying Line Types

When working with layouts for elements like lines, tees, and bends, you can easily change the metallization used. Every element that draws a line has a Line Type setting. These line types are configured for each PDK. Changing the line type also changes the electrical characteristics of the lines, specifically the metal thickness. If the PDK is set up correctly, changing the line type also changes the substrate used for that model. For this to work, the line type names and substrate names must match. For this process, there are three substrates whose names match the names of the line types available: "Plated_Metal_Line", "Metal_1", and "Metal_2".

To change an element line type:

  1. Select the item in the layout.

  2. Right-click and choose Shape Properties.

  3. In the Cell Options dialog box, change the Line Type.

To change line types:

  1. Open the 2D and 3D layouts for the "Distributed_input_match" schematic. Tile the windows vertically for easy viewing by choosing Window > Tile Vertical.

  2. In the 2D layout, choose Draw > 3D Clip Area and then click and drag to create a box around the upper left capacitor and lines, as shown in the following figure.

    With this object drawn, the 3D layout view shows only the shapes in this region. The remainder of this example is easier if you zoom into this same area in the 2D view.

    The 3D layout displays as follows.

  3. In the schematic, select the line immediately to the right of the capacitor as shown in the following figure. Note the MSUB.

    Right-click and choose Shape Properties to display the Cell Options dialog box. Change the Line Type from Metal 2 to Plated Metal Line and click OK.

    The 2D layout displays as follows.

    The 3D layout displays as follows.

    Notice that the line is using all three processing layers for the layout instead of just one as shown in the previous figures. Also note that the MSUB parameter name has changed to the proper substrate. NOTE: You can change the MSUB model parameter to a different line and see the line type change in the layout.

Using Automatic Interconnect

Using multiple line types in a process adds design complexity when connecting between lines that use different Line Types, or between lines and devices like capacitors, resistors, inductors and transistors. For example, consider how lines connect to a capacitor in the provided example: The top plate of the capacitor uses Metal 2 and the bottom plate uses Metal 1. There are three line types in this process, Metal 1 (just Metal 1 layer), Metal 2 (just Metal 2 layer), and Plated Metal Line (Metal 1, Metal 2, and Dielectric Via layers). If you connect a line on Metal 1 to the Metal 2 side of the capacitor, you must draw additional shapes to make a proper connection. This is handled automatically in the NI AWR PDKs. Each PDK has automatic interconnect (sometimes called "Bridge Code"), that draws the correct connecting shapes at the ends of lines (for example, MLIN, MTRACE2, or MCTRACE). The goal of the automatic interconnect is to handle connections between every combination of Line Type and from every Line Type to every component, so that all of these connections are design rule correct. Note that automatic interconnect is drawn from the top down. If, for example, a line in the lower level of a hierarchy connects to the cap in the higher level, no automatic interconnect is drawn, which is why you must connect a line to the cap at the higher level also. See “Working Through Hierarchy” for details on automatic interconnect and hierarchy.

The following example starts with the same 2D and 3D layouts used previously and shows the use of automatic interconnect.

  1. Notice that the line on the left side of the capacitor is drawing on Metal 2, which is the same metal for the top plate of the capacitor, so no special drawing is needed.

  2. Change the Line Type of that line to Metal 1 and view the layout.

    Notice that the layout changed on the line to the left of the capacitor. A via is drawn for the proper transition from Metal 2 to Metal 1.

  3. Change the Line Type of the line on the right side of the capacitor to Metal 2 and view the layout.

    Notice that the layout changed on the line right to the of the capacitor. This time the proper transition is drawn from Metal 1 to Metal 2.

  4. Open the "Distributed_input_match" schematic and zoom in near port 1. Select both port 1 and the MLIN connected to it. Press the Ctrl key while dragging the elements to the left to break the connection between the line and the capacitor. The schematic should display as follows.

    Since there is no electrical connection between the capacitor and the line, there is no transition from Metal 1 to Metal 2, so the automatic interconnect does not draw the connection.

    This proves that the layout draws properly, based on how the elements are connected in the schematic.

  5. Change both line types on either side of the capacitor back to Metal 2 and reconnect the port and MLIN to the schematic before continuing.

Using Layout Snapping

In the NI AWR Design Environment software, layouts are automatically generated for models that are configured with layout cells. For MMIC design using PDKs, each element should have a layout configured. The layout does not automatically know how to position each model's layout cell relative to the others, so the snapping process is required to move the individual components together to connect them. To understand snapping, you must first understand layout faces.

Each layout cell must define where connections are allowed. There are two types of connection locations allowed: area pins and faces. Area pins allow connections at any location within an area and are not used often in MMIC design. Faces allow a connection at various locations along the face. The location depends on settings for each face. Connecting to the center is the most common setting. Faces have numbers that correspond to model node numbers. When nodes of models are connected in a schematic, the layout knows which faces must be connected. If the faces properly overlap, no rat line displays in the layout. If they do not properly overlap, a rat line displays in the layout to indicate which element faces must be snapped together to correct the layout.

With layout snapping, layout objects are automatically moved to minimize rat lines in the layout. You snap a layout together by first selecting the items to snap (if Manual snap for selected objects only is selected as the Snap together option on the Layout Options dialog box Layout tab), and then choosing Edit > Snap Objects > Snap Together or clicking the Snap Together button on the toolbar. There are several issues to consider when using snapping:

  • There are different snapping modes, manual and automatic. See “Layout: Snapping Strategy” for details on choosing the correct snapping mode, which is typically determined by the completeness of your layout. This project uses the Manual snap for selected objects only option.

  • The order in which objects are moved during snapping depends on several issues:

    1. You can specify any layout object as the anchor by selecting the object, right-clicking and choosing Shape Properties to display the Cell Options dialog box. Click the Layout tab and select the Use for anchor check box.

      When an item is anchored, it displays with a red circle with crosshairs through it as shown in the following figure.

      Snapping starts with any anchored items. If a layout has only one anchor, that item does not move during snapping.

    2. For either of the snapping modes where all elements are snapped (Auto snap on parameter changes and Manual snap for all objects), the anchored items remain fixed and all others can potentially move. If there is no anchor, the first item found is fixed. In the snapping mode for selected items (Manual snap for selected objects only), if there are no anchored items in the selected items, the first item selected stays fixed.

  • When faces are snapped together, by default they snap to the center of each face. Settings for each face determine the location in which that face snaps. You can access these settings by selecting a layout object, right-clicking and choosing Shape Properties to display the Cell Options dialog box. Click the Faces tab and select the face you want to specify from the Face drop-down menu, then in the Face Justification section you change the face snapping location. When changing the face, position the dialog box so you can view the layout for the effects of the different settings. For example, the following figure shows Face 1 of an MLIN with Center justification.

    The blue line in the layout with the small vertical line in the middle of the face shows the face currently selected, and the small vertical line shows the face justification. For example, the following figure shows the same face with Bottom justification.

    Notice how the vertical line is now on the right side of the face.

    The following figure shows the Face set to "2". The blue line is now drawn on the other side of the MLIN.

  • Snapping can also be used hierarchically by choosing Edit > Snap All Hierarchy. This command starts at the lowest level of hierarchy for the current layout, snaps those layouts together, and then progressively works up through the hierarchy. A layout setting controls whether or not rat lines from lower levels of hierarchy display at the current level. To specify this setting, choose Layout > Layout Mode Properties to display the Layout Editor Mode Settings dialog box. In the Drawing options section of the dialog box, select Draw all rat lines, as shown in the following figure.

  • In some situations more than two elements are connected to a node. In this case, snapping moves all of the faces to the same location, which is typically not the correct location for each item. Fortunately, there are face settings to control how snapping functions in this scenario. See “Using More Than Two Connections at a Node” for details. In this example, this technique is used for the capacitors in the bias networks for the input and output distributed matching network layouts as well as in the "device" schematic for the two lines connecting to the source of the transistor.

Many of the snapping and faces concepts can be further explained with an example. In the "Distributed_output_match" layout, there is a narrow line feeding a capacitor after an inductor in the bias path.

Instead of centering this line on the cap, you can align it with the left edge of the capacitor. To align the capacitor and line:

  1. Open the layout for the "Distributed_output_match" schematic.

  2. Select the line between the capacitor and inductor, right-click and choose Shape Properties to display the Cell Options dialog box, then click the Faces tab.

  3. Make sure your options match those in the following figure.

    Notice that the vertical line showing the face justification displays on the left side of the line.

  4. Click OK to accept this change.

  5. You must also change the capacitor face by selecting the capacitor, right-clicking and choosing Shape Properties to display the Cell Options dialog box.

  6. Click the Faces tab and make sure your options match those in the following figure.

    Notice that the vertical line showing the face justification displays on the left side of the line.

  7. Click OK to accept this change.

    At this point, you can snap this subcircuit together, although the top level also needs to be snapped together. Instead, you can do this all from the top level.

  8. Open the "Distributed Design" schematic layout. Press Ctrl + A to select all of the layout items, then choose Edit > Snap All Hierarchy to snap together the top layout, with the capacitor moved. The "Distributed_output_match" schematic layout is also snapped together and the line and capacitor are aligned along their left edge.

You can close this project without saving, and reopen it to continue with the remaining examples. If you do not do so, the following steps still work, however some of the figures are slightly different due to the alignment of the line and the capacitor.

Snapping to Fit

In general, when a layout has a rat line, you can select an element on either side of the rat line and perform a "Snap to fit" operation by choosing Edit > Snap to fit or clicking the Snap to fit button on the Schematic Layout toolbar. During this operation the element attempts to adjust its parameters to resolve the rat line. Only certain elements can change their length with this command. The toolbar button is grayed if the item you select does not support this mode. The common models supported for snap to fit operations are single lines, trace elements, and iNets.

In this example, the MTRACE2 elements feeding the bias pads are a good place to demonstrate the usefulness of a "Snap to fit" operation.

  1. In the "Distributed Design" layout, select the layout for the input matching network, right-click and choose Edit in Place.

  2. Drag the bond pad to the right, as shown in the following figure.

    Notice the rat line that displays between the MTRACE and the bond pad.

  3. Select the MTRACE2 line feeding the bond pad and then click the Snap to fit button on the toolbar to see the layout change to fill in the space between the line and pad. Additionally, the length of the MTRACE2 also changes, so the simulation results reflect this changed length. (NOTE: The "Snap to fit" operation cannot change the shape of a TRACE element, it only adjusts segment lengths.)

Using Intelligent Parameter Syntax

Sometimes when designing, you want to make symmetrical layouts. You can use hierarchy to accomplish this, however, hierarchy can be excessive. You can also use variables to tie two components to the same value, although this presents other problems, including:

  1. Variables are prone to mistakes (typing in the wrong values results in errors).

  2. Variables can be difficult to find, especially in a complex design. Typically, groups of equations are created and they might be placed far away from the component that uses them.

  3. Parameters tied to variables cannot be edited in layout.

Intelligent parameter syntax can help solve this problem. See “Using Intelligent Parameter Syntax” for details on setting up this syntax.

The lines feeding the vias on the source of the FET are a good example of this case. The "device" schematic uses this syntax for the right MTRACE2 element in the schematic, as shown in the following figures (NOTE: For the MTRACE2 elements, the secondary parameters RB and DB must also use this syntax).

Now, you need only edit the shape (for example, length and bends) of the master element, just as you would edit any element. The slave element (with parameters that match the master) automatically matches any changes in the master. To edit the master and see the effect on the slave element:

  1. Double-click the master MTRACE2 element, which is the line above the FET.

  2. Click the center of the middle horizontal line and drag it up, as shown in the following figure.

  3. Release the mouse, and both the top and bottom lines are changed, as shown in the following figure.

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