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Piecewise Linear Voltage Source: V_PWL

Symbol

Summary

This signal source is superseded and should be replaced with one of the following: AC_V for voltage sources, AC_I for current sources, or PORT_SRC for ports, with the Signal parameter set to this signal type.

The period for tone 1 sources is the inverse of the specified simulation frequency; see “Frequency Sweep Control” for details.

Summary

The behavior of V_PWL is similar to that of the PWL source in SPICE. The voltage is specified by the pairs of time-voltage values (TIME[i], VOLTAGE[i]). The values of voltage between these time instances are obtained by linear interpolation. The fundamental frequency is equal to that specified for the schematic containing the port.

Parameters

Name Description Unit Type Default
ID Voltage source ID Text V1
TIME Vector of time values Time User has to override the default
Voltage Vector of voltage values Voltage User has to override the default
WINDOW Window type   DEFAULT[1]
DCVal DC value (used for DC analysis) Voltage 0

[1] Window type options are none (NONE), Lanczos (DEFAULT, ref [1]), Triangular (TRIANG), Hanning (HANN), Hamming (HAMM), Blackman (BLACK). See I_PLS for additional details on the WINDOW parameter.

Parameter Details

The dimension of TIME and SIG vectors must be identical. This dimension should be greater than 3, as at least 4 points are required to specify a meaningful PWL waveform. An error message is issued if one of these conditions is not satisfied, and the model is rejected. The values of time should be sorted in ascending order (TIME[i+1]>TIME[i]. Discontinuities in the voltage value are not allowed (do not specify two different voltage values for the same time instance).

Implementation Details

Note that the signal needs to be periodic with the period equal to that of the fundamental frequency, otherwise results may be unexpected. The accuracy of the simulation results depends on the number of the harmonics of the fundamental frequency. This number of harmonics is determined from the options for the schematic containing this source.

Layout

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

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