Go to www.awrcorp.com
Back to search page Click to download printable version of this guide.

Differential Vias in Multilayer Board: VIAMD

Symbol

Summary

VIAMD models a pair of identical coupled vias in a multilayer printed circuit board. This model assumes that all dielectric layers crossed by vias are separated by infinite perfect conducting grounded planes. Each ground plane has two antipads and vias pass through the center of each antipad. Capture pads are located at the via ends. The environment of each capture pad is user-controlled via model parameters. These parameters implement all typical via configurations: Thru, buried, and blind. You can take a pad out from one or both via ends and implement a series connection of several vias.

It is imperative for vias to cross at least one dielectric layer with ground planes with an antipad at the top and bottom.

Multilayer via analysis is based on the theory of long cylindrical antenna excited by a frill of magnetic current radiating in a parallel plate waveguide and on the theory of monopole radiating into a parallel plate waveguide. This model also uses quasi-static FEM analysis for accurate evaluation of capacitances of complex conducting configurations in a multilayered dielectric.

Topology

Figure 1. Basic stackup

Figure 2. Option "Board Top"

Figure 3. Option "Inside Board with Pad"

Figure 4. Option "Inside Board No Pad"

Figure 4_1. Option "Inside Antipad no Pad"

Figure 4_2. Option "Inside Antipad with Pad"

Figure 4_3. Option "Inside Board & Antipad with Pad"

Parameters

Name Description Unit Type Default
ID Element ID Text PKG1
N Number of dielectric layers   1
DV External diameter of via hole Length W[1]
DA Diameter of antipad Length L[1]
DPT Diameter of top capture pad Length L[1]
DPB Diameter of bottom capture pad Length L[1]
S Distance between via axes Length L[1]
TP Thickness of capture pad Length T[1]
H Heights of dielectric layers (vector) Length {0.1 mm}
Er Relative dielectric constants of dielectric layers (vector)   {1}
Rho Via metal bulk resistance relative to gold   1
TopCap Switch "Board Top"/"Inside Board with Pad/Inside Board No Pad/Inside Antipad No Pad" Length "Board Top"
BotCap Switch "Board Top"/"Inside Board with Pad/Inside Board No Pad/Inside Antipad No Pad" Length "Board Top"
*Acc Switch "Default/High"   "Default"
*Update_Pad_in_Antipad Switch "No/Yes"   "No"

[1] User-modifiable default. Modify by editing under $DEFAULT_VALUES in the default.lpf file in the root installation directory. See “Default Values” for details.

* indicates a secondary parameter

Parameter Details

N. This parameter defines the number of dielectric layers in a multilayered board separated by ground planes (see the "Basic stackup" figure in the "Topology" section). NOTE: Only layers from the "Basic stackup" are counted toward N. The actual number of layers VIAM uses depends on the options selected with the TopCap and BotCap parameters (see the following details for these parameters.) Note that VIAM does not allow a zero value of N (see "Parameter Restrictions and Recommendations".)

DPT, DPB. The diameters of the capture pads attached to the via top ends (Ports #1 and #3) and to the via bottom ends (Ports #2 and #4). Certain options of the TopCap and BotCap parameters imply that the respective pad is missing.

H, Er. These vector parameters define the height and dielectric constant of every dielectric layer in the board setup. Note that these vectors always include heights and dielectric constants of layers defined by the TopCap and BotCap parameters. TopCap adds values to the vector head while BotCaps adds values to the vector tail. You must provide correct values for each layer the model uses.

TopCap, BotCap. Each of these switching parameters has four user-selectable options. These options allow the addition of via caps of various configurations to each via end of the basic multilayer configuration presented in the "Basic stackup" figure in the "Topology" section.

TopCap defines the configuration of the via caps at Ports #1 and #3 and BotCap defines the configuration of the via caps at Ports #2 and #4.

All available configuration/options are presented in the "Topology" section in figures with corresponding captions. The "Board Top" option requires the addition of one more value to vectors H and Er in addition to the layer values needed for "Basic stackup". The "Inside Board with Pad " and "Inside Board no Pad" options require the addition of two more values to vectors H and Er. The "Inside Antipad no Pad" option does not add any values to H and Er because it leaves the via end "as is" in the "Basic stackup." The "Inside Antipad with Pad" and "Inside Board & Antipad with Pad" options insert a capture pad inside the top or bottom antipad; "Inside Antipad with Pad" (as well as "Inside Antipad no Pad") do not add any values to H and Er. The "Inside Board & Antipad with Pad" option requires the addition of one more value to vectors H and Er in addition to the layer values needed for "Basic stackup".

Note that TopCap and BotCap can be set independently to different options. The size of vectors H and Er are defined by both selected options.

Acc. The default value of the Acc parameter excludes the contribution of higher modes into the via model. Setting Acc=High adds the evaluation of series representing the contribution of high modes and slightly increases simulation time. In most cases Acc=Default provides sufficient accuracy, but for very long vias crossing many dielectric layers and for tightly coupled vias (small S), Acc=High might be beneficial.

Update_Pad_in_Antipad. This parameter has an effect only if the TopCaP or BotCap parameter values are either "Inside Antipad with Pad" or "Inside Board & Antipad with Pad". The default value of the parameter Update_Pad_in_Antipad=No neglects the contribution of excess inductance of a pad located inside antipad. Setting Update_Pad_in_Antipad=Yes adds this excess inductance, improving accuracy at higher frequencies but slightly increasing simulation time due to use of the involved numerical algorithms. At lower frequencies (for example, less than 4-5 GHz for a typical PCB) the default value of "Update_Pad_in_Antipad" is sufficient, but at higher frequencies Update_Pad_in_Antipad=Yes might be beneficial.

Parameter Restrictions and Recommendations

  1. The number of layers N in Basic stackup must be 1<=N<=30. Note that N=0 is not allowed for VIAMD.

  2. This model assumes that only dominant mode TMo propagates in each layer over all frequency sweep. The heights of all layers are checked for normal operation below the cutoff frequency of the higher mode propagating in respective parallel-plate waveguide. If the frequency exceeds the cutoff threshold the model generates an error and reports the highest sweep frequency allowed for the specified separation between ground planes.

Implementation Details

The via is modeled as a set of segments contained within ground-separated dielectric layers. Each segment is modeled as cylindrical antenn dipole radiating between perfectly conducting parallel plates. Modeling techniques used are based on publications [1]-[4]. Via cap capacitance is treated by means of a quasi-static FEM technique based on [5], [6]. Port reference planes are located at the centers of capture pads. Ports #1 and #3 are associated with the top end of the via and ports #2 and #4 are associated with the bottom end of the via.

Layout

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

Recommendations for Use

See examples of various via implementations in the VIAM model documentation (note that examples for N=0 are not valid for VIAMD).

This model uses a disk cache, so if a project contains multiple instances of identical VIAMD only one instance simulates and saves results to the cache, and all identical (having the same parameter set) VIAMD simply fetch these results from cache. Note that the cache keeps saved data and any project on the same computer that contains VIAMD with the same set of parameters reuses the cached data.

References

[1] Qizheng Gu, Y. Eric Yang, and M.Ali Tassoudji, "Modeling and Analysis of Vias in Multilayered Integrated Circuits," IEEE Trans. on Microwave Theory and Tech., vol. 41, February 1993, pp. 206-214

[2] Qizheng Gu, M.Ali Tassoudji et al, "Coupled Noise Analysis for Adjacent Vias in Multilayered Digital Circuits," IEEE Trans. on Circ. and Syst., vol. 41, December 1994, pp. 796-804

[3] B.Tomasic and A. Hessel, "Linear Array of Coaxially Fed Monopole Elements in a Parallel Plate Waveguide," IEEE Trans. on Antennas and Prop., vol. 36, April 1988, pp. 449-462

[4] M. Goldfarb and R. Pucel, "Modeling Via Hole in Microstrip," IEEE Microwave and Guided Wave Lett., vol. 1, June 1991, pp. 135-137

[5] FEMM (by David Meeker) home page: https://www.femm.info/wiki/HomePage

[6] Jonathan Richard Shewchuk. Triangle. A Two-Dimensional Quality Mesh Generator and Delaunay Triangulator. Follow this link for information and download: http://cs.cmu.edu/~quake/triangle.html

Legal and Trademark Notice