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Multilayer PCB Via with Multiple Connections: VIAM3

Symbol

Summary

VIAM3 models a via with multiple connections in a multilayer PCB defined by a user-supplied stackup. VIAM3 is a dynamic model, its symbol size is defined by a number of connections. This model assumes that all dielectric layers crossed by the via (excluding dielectric layers carrying dedicated signal trace layers) are separated by infinite perfect conducting grounded planes. Each ground plane has an antipad and the via passes through the center of each antipad. Capture pads are located at each trace layer; you select PCB trace layers where the via connects to the board. The environment of each capture pad is controlled by model and stackup parameters. Model parameters allow implementation of all typical via configurations: through, buried, and blind.

Multilayer via analysis is based on the theory of a long cylindrical antenna excited by a frill of magnetic current radiating in a parallel plate waveguide, and on the theory of monopole radiating into a parallel plate waveguide. This model also uses quasi-static FEM analysis for accurate evaluation of capture cap capacitances in various environmental configurations.

Topology

Figure 1. Configuration On_Gnd

Figure 2. Configuration On_Sig. Through via

Figure 3. Configuration On_Sig. Blind via

Figure 4. Configuration On_Sig. Buried via

Parameters

Name Description Unit Type Default
ID Element ID Text V1
Gnd_Sig Selection of via configuration (Switch On_Gnd/On_Sig)   On_Gnd
NC Number of connections   4
CLi, i=1..NC - number of via connection Number of trace layer of connection #n   1
DV External diameter of via hole Length W[1]
DA Diameter of antipad Length L[1]
DP Diameter of capture pad Length L[1]
DPT Diameter of top (bond) capture pad Length L[1]
ViaTop Trace layer at via top end   1
ViaBot Trace layer at via bottom end   4
TP Average thickness of trace metal Length T[1]
Rho Average trace metal bulk resistance relative to gold   1
Acc Accuracy of evaluation of via segment formulation (Switch Default/High)   Default
STACKUP Substrate Definition Text STACKUP1[2]

[1] User-modifiable default. Modify by editing under $DEFAULT_VALUES in the default.lpf file in the root installation directory. See “Default Values” for details.

[2] Modify only if schematic contains multiple substrates. See “Using Elements With Model Blocks” for details.

* indicates a secondary parameter

Parameter Details

Gnd_Sig. This is a selector/switch that allows you to choose from two configurations of arrangement of PCB trace layers available for setting the connection to a via.

First configuration. implies that all trace layers are located only on ground planes and each via segment crossing the ground plane is surrounded by an annular antipad; so every signal trace that connects to the via capture pad crosses the respective antipad at least once. This configuration is selected by setting GnD_Sig = On_Gnd

Second configuration. allows the signal traces connecting to the via capture pads to be located either on ground planes or on dedicated signal layers. Similar to the first configuration, every connecting signal trace located on the ground plane needs to cross the antipad to reach the capture pad. On the contrary, a dedicated signal later allows the connecting signal trace to reach the via capture pad directly. This configuration stipulates the predefined sequence order of ground planes and dedicated signal layers, namely, that ground plane trace layers alternate with dedicated signal layers. In this configuration, each dedicated signal layer (as well as the respective via capture pad) must be sandwiched between two adjacent dielectric layers. Two ground planes must be placed on the top and bottom of this sandwich. Similar to the first configuration, these ground planes are also available for setting via connections. This configuration is selected by setting GnD_Sig = On_Sig.

NC. Defines the total number of via connections to the board at various trace layers. Note that the permissible value of NC is limited by the ViamTop and ViaBot parameters.

CLn. This dynamic parameter contains a number of trace layers where the n-th connection to a via is implemented. You must specify the NC connections exactly. The number of connection trace layers must be listed in strictly ascending order from via top to bottom.

DP, DPT. DP is the diameter of all inner (inside board) capture pads. DPT is the diameter of a bond pad located on the top/bottom trace layer. Note that the diameter of inner pad DP is limited by antipad diameter DA, while this limitation does not apply to the diameter of a bond pad DPT.

ViaTop, ViaBot. The numbers of upper (ViaTop) and lower (ViaBot) trace layers crossed by a via. If NT is defined as the number of PCB trace layers, then setting ViaTop = 1 and ViaBot = NT defines a through via, ViaTop = 3 and ViaBot = NT defines a blind via, and ViaTop = 5, ViaBot = 7 defines a buried via.

TP. The average thickness of trace layers.

Rho. The average value of bulk resistance (relative to gold) of trace and via barrel metals .

Acc. In certain situations setting Acc = High may improve the accuracy of via modeling, but in most cases Acc = Default provides adequate accuracy.

STACKUP. VIAM3 uses stackup in place of a traditional substrate, and gets from the stackup: thicknesses, dielectric constants, and loss tangents of PCB dielectric layers. The average values of PCB trace thicknesses and bulk resistances of trace and via barrel metals are provided by the TP and Rho parameters.

Parameter Restrictions and Recommendations

  1. Number of via connections (NC) must be less than or equal to ViaBot - ViaTop + 1.

  2. Number of connection trace layers must be listed in strictly ascending order from via top to bottom.

  3. Diameter of the inner capture pad (DP) must be less than the diameter of the antipad (DA). No limit is applied to the bond (top or bottom) capture pad (DPT).

  4. This model assumes that only dominant mode TMo propagates in each layer over all frequency sweeps. The heights of all layers are checked for normal operation below the cutoff frequency of the higher mode propagating in respective parallel-plate waveguide. If the evaluation frequency exceeds the cutoff threshold, the model generates an error and reports the highest sweep frequency allowed for the specified separation between ground planes.

Implementation Details

The via is modeled as a set of segments contained within ground-separated dielectric layers. Each segment is modeled as a cylindrical antenna dipole radiating between perfectly conducting parallel plates. Modeling techniques used are based on publications [1]-[4]. Via cap capacitance is treated by means of a quasi-static FEM technique based on [5] and [6]. Port reference planes are located at the centers of the capture pads.

Layout

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

Recommendations for Use

The following are examples of via implementation per various settings of the configuration parameter Gnd_Sig. Note that in the "Topology" section, dashed lines in the figures indicate the boundaries of dielectric layers where the signal trace layers are located, and bold black horizontal rectangles indicate ground planes (where signal traces may also be located). The following designates the total number of stackup trace layers as NT.

  1. Setting Gnd_Sig = On_Gnd assumes that all trace layers are located on ground planes, and all capture pads are inside antipads (see "Topology", Figure 1)

  2. Setting Gnd_Sig = On_Sig, ViaTop = 1, and ViaBot = NT assumes that ground plane trace layers alternate with dedicated signal layers and the via is a through via (see "Topology", Figure 2). A through via automatically accepts "board top caps" on the top and bottom of the pad stack. These caps model end via segments and end bond pads as elements of microstrip transmission lines (see "Topology", Figure 2).

  3. Setting Gnd_Sig = On_Sig, ViaTop = 1, and ViaBot < NT (or ViaTop > 1 and ViaBot = NT) assumes that ground plane trace layers alternate with dedicated signal layers and the via is a blind via (see "Topology", Figure 3). A blind via automatically accepts one "board top cap" on top and an "inside board cap" on the bottom (or "inside board top cap" on top and "board top cap" on bottom) of the pad stack. The board top cap is similar to the one a through via has. The inside board cap models the end via segment as a monopole radiating into the parallel-plane waveguide. (see "Topology", Figure 3).

  4. Setting Gnd_Sig = On_Sig, ViaTop > 1, and ViaBot < NT assumes that ground plane trace layers alternate with dedicated signal layers and the via is a buried via (see "Topology", Figure 4). A buried via automatically accepts one "board top cap" on top and an "inside board cap" on bottom (or "inside board top cap" on top and "board top cap" on bottom) of the pad stack. The board top cap is similar to the one a through via has. The inside board cap models the end via segment as a monopole radiating into the parallel-plane waveguide. (see "Topology", Figure 4).

  5. On simulation , VIAM3 outputs information about connection layers specified by the CLn parameters (for Gnd_Sig = On_Sig only). This information helps you verify if the trace layer assigned by the CLn parameter is a ground plane or dedicated signal layer.

  6. VIAM3 uses a disk cache, so if a project contains multiple instances of identical VIAM, only one instance simulates and saves results to the cache, and all identical (having the same parameter set) VIAMs simply fetch these results from the cache. Note that the cache keeps saved data, and any project on the same computer that contains VIAM with the same set of parameters reuses the cached data.

References

[1] Qizheng Gu, Y. Eric Yang, and M.Ali Tassoudji, "Modeling and Analysis of Vias in Multilayered Integrated Circuits," IEEE Trans. on Microwave Theory and Tech., vol. 41, February 1993, pp. 206-214

[2] Qizheng Gu, M.Ali Tassoudji et al, "Coupled Noise Analysis for Adjacent Vias in Multilayered Digital Circuits," IEEE Trans. on Circ. and Syst., vol. 41, December 1994, pp. 796-804

[3] B.Tomasic and A. Hessel, "Linear Array of Coaxially Fed Monopole Elements in a Parallel Plate Waveguide," IEEE Trans. on Antennas and Prop., vol. 36, April 1988, pp. 449-462

[4] M. Goldfarb and R. Pucel, "Modeling Via Hole in Microstrip," IEEE Microwave and Guided Wave Lett., vol. 1, June 1991, pp. 135-137

[5] FEMM (by David Meeker) home page: https://www.femm.info/wiki/HomePage

[6] Jonathan Richard Shewchuk. Triangle. A Two-Dimensional Quality Mesh Generator and Delaunay Triangulator. Follow this link for information and download: http://cs.cmu.edu/~quake/triangle.html

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