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Multiport Single Via in Multilayer Board: VIAM2



VIAM2 models an isolated via in a multilayer printed circuit board. Similar to VIAM, VIAM2 assumes that all dielectric layers crossed by the via are separated by infinite perfect conducting grounded planes. VIAM2 differs from VIAM in its ability to attach multiple VIAMC elements representing per-layer coupling between two VIAM2 elements. VIAM2 is a dynamic model; its schematic symbol changes (adds/removes terminals) when the number of board layers changes. See VIAM for additional details.




Name Description Unit Type Default
ID Element ID Text V1
N Number of dielectric layers   1
DV External diameter of via hole Length W[1]
DA Diameter of antipad Length L[1]
DPT Diameter of top capture pad Length L[1]
DPB Diameter of bottom capture pad Length L[1]
TP Thickness of capture pad Length T[1]
H Heights of dielectric layers (vector) Length {0.1 mm}
Er Relative dielectric constants of dielectric layers (vector)   {1}
Rho Via metal bulk resistance relative to gold   1
TopCap Switch "Board Top"/"Inside Board with Pad/Inside Board No Pad/Inside Antipad No Pad" Length "Board Top"
BotCap Switch "Board Top"/"Inside Board with Pad/Inside Board No Pad/Inside Antipad No Pad" Length "Board Top"
*Acc Switch "Default/High"   "Default"

[1] User-modifiable default. Modify by editing under $DEFAULT_VALUES in the default.lpf file in the root installation directory. See “Default Values” for details.

* indicates a secondary parameter

Parameter Details

N. This parameter defines the number of dielectric layers in a multilayered board separated by ground planes (see the "Basic stackup" figure in the "Topology" section of VIAM). It is important to note that only layers from the "Basic stackup" are counted toward N. The actual number of layers VIAM2 uses depends on the options selected with the TopCap and BotCap parameters (see the following details for these parameters.) Note that (contrary to VIAM) VIAM2 does not allow a zero value of N (see "Parameter Restrictions and Recommendations".)

DPT, DPB. The diameters of the capture pads attached to the via top end (Port #1) and to the via bottom end (Port # N+2). Certain options of the TopCap and BotCap parameters imply that the respective pad is missing.

H, Er. These vector parameters define the height and dielectric constant of every dielectric layer in the board setup. Note that these vectors always include heights and dielectric constants of layers defined by the TopCap and BotCap parameters. TopCap adds values to the vector head while BotCap adds values to the vector tail. You must provide correct values for each layer the model uses.

TopCap, BotCap. Each of these switching parameters has four user-selectable options. These options allow the addition of via caps of various configurations to each via end of the basic multilayer configuration presented in the "Basic stackup" figure in the "Topology" section.

TopCap defines the configuration of the via cap at Port #1 and BotCap defines the configuration of the via cap at Port #N+2.

All available configuration/options are presented in the "Topology" section (see VIAM) in figures with corresponding captions. The "Board Top" option requires the addition of one more value to vectors H and Er in addition to the layer values needed for "Basic stackup"; the "Inside Board with Pad " and "Inside Board no Pad" options require the addition of two more values to vectors H and Er; the "Inside Antipad no Pad" option does not add any values to H and Er because it actually leaves the via end "as is" in "Basic stackup."

Note that TopCap and BotCap can be set independently to different options. The size of vectors H and Er are defined by both selected options.

Acc. The default value of this parameter excludes the contribution of higher modes into the via model. Setting Acc=High adds the evaluation of series representing the contribution of higher modes and slightly increases simulation time. In most cases Acc=Default provides sufficient accuracy but for very long vias crossing many dielectric layers Acc=High might be beneficial. Note that the value of Acc should match the value of Acc set for attached VIAMC elements.

Parameter Restrictions and Recommendations

  1. The number of layers N in the Basic Stackup must be 1<=N<=30. Note that N=0 is forbidden for VIAM2 but allowed for VIAM.

  2. This model assumes that only dominant mode TMo propagates in each layer over all frequency sweep. The heights of all layers are checked for normal operation below the cutoff frequency of the higher mode propagating in respective parallel-plate waveguide. If the evaluation frequency exceeds the cutoff threshold the model generates an error and reports the highest sweep frequency allowed for the specified separation between ground planes.

Implementation Details

The via is modeled as a set of segments contained within ground-separated dielectric layers. Each segment is modeled as cylindrical antenna dipole radiating between perfectly conducting parallel plates. Modeling techniques used are based on publications [1]-[4]. Via cap capacitance is treated by means of a quasi-static FEM technique based on [5], [6]. Port reference planes are located at the centers of capture pads. Port #1 is associated with the top end of the via and Port #N+2 is associated with the bottom end of the via. Port #2..#N+1 are coupling ports. The only element that should be connected to any of these ports is VIAMC (see the example in the "Recommendations for Use" section).


This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

Recommendations for Use

  1. If no coupling, VIAMC elements are connected to Ports #2..#N+1, then VIAM2 behaves similar to the VIAM element.

  2. To provide the most accurate evaluation of coupling, all VIAM2 elements connected with VIAMC elements must have identical parameters DV, DA, and Acc.

  3. Restriction N>=1 (at least one dielectric layer bounded by two ground planes) is mandatory because each VIAMC element evaluates coupling due to TMo mode propagating in the respective layer. VIAM2 assumes that this coupling is predominant and neglects coupling between via caps (see VIAM, VIAMD).

  4. Building a network of coupled vias requires one VIAMC element per layer, per each pair of VIAM2 elements included in a coupled set of vias. For efficiency, a good practice may be to create separate subcircuits for each layer and connect VIAM2 elements to subcircuits using named connectors (NCONN) and named ports (PORT_NAME). See the following example.

  5. This model uses a disk cache, so if a project contains multiple instances of identical VIAM2 only one instance simulates and saves results to the cache, and all identical (having the same parameter set) VIAM2 elements simply fetch these results from cache. Note that the cache keeps saved data, and any project on the same computer that contains VIAM2 with the same set of parameters reuses the cached data.

The following example demonstrates how coupling between vias in a PCB may affect coupling between signal traces. In this example, three edge-coupled traces on top of a PCB board connect to three edge-coupled striplines inside the board. The board is comprised of four FR-4 layers. Ground planes separate dielectric layers and the bottom of the board is also metallized. Microstrips and striplines are connected with three blind vias. Note that captions reside under the figures.

Figure 1. Via Cross View

Figure 2. Via Top View

The following are material properties and dimension denotations (dimensions in mils). t1, t2 etc. are loss tangents.

Figure 3. Dimensions in mils

Figure 4. Schematic: Three coupled lines

Figure 5. Subcircuit with coupled vias

Simulation results demonstrate losses for cases where vias are not accounted for, when vias are accounted for but coupling between vias is neglected, and when coupling between vias is factored in.

Figure 6. Simulation results: S41 in dB - Insertion loss

Figure 7. Simulation results: S61 in dB - Coupling loss


[1] Qizheng Gu, Y. Eric Yang, and M. Ali Tassoudji, "Modeling and Analysis of Vias in Multilayered Integrated Circuits," IEEE Trans. on Microwave Theory and Tech., vol. 41, February 1993, pp. 206-214

[2] Qizheng Gu, M.Ali Tassoudji et. al., "Coupled Noise Analysis for Adjacent Vias in Multilayered Digital Circuits," IEEE Trans. on Circ. and Syst., vol. 41, December 1994, pp. 796-804

[3] B. Tomasic and A. Hessel, "Linear Array of Coaxially Fed Monopole Elements in a Parallel Plate Waveguide," IEEE Trans. on Antennas and Prop., vol. 36, April 1988, pp. 449-462

[4] M. Goldfarb and R. Pucel, "Modeling Via Hole in Microstrip," IEEE Microwave and Guided Wave Lett., vol. 1, June 1991, pp. 135-137

[5] FEMM (by David Meeker) home page: https://www.femm.info/wiki/HomePage

[6] Jonathan Richard Shewchuk. Triangle. A Two-Dimensional Quality Mesh Generator and Delaunay Triangulator. Follow this link for information and download: http://cs.cmu.edu/~quake/triangle.html

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