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Single Via in Multilayer Board: VIAM

Symbol

Summary

VIAM models an isolated via in a multilayer printed circuit board. This model assumes that all dielectric layers crossed by the via are separated by infinite perfect conducting grounded planes. Each ground plane has an antipad and the via passes through the center of each antipad. Capture pads are located at via ends. The environment of each capture pad is user-controlled via model parameters. These parameters allow implementation of all typical via configurations: through, buried, and blind. You can take a pad out from one or both via ends and implement a series connection of several vias.

It is imperative that the via cross at least one ground plane with antipad.

Multilayer via analysis is based on the theory of long cylindrical antenna excited by a frill of magnetic current radiating in a parallel plate waveguide, and on the theory of monopole radiating into a parallel plate waveguide. This model also uses quasi-static FEM analysis for accurate evaluation of capacitances of complex conducting configurations in a multilayered dielectric.

Topology

Figure 1a. Basic stackup (N=1)

Figure 1b. Basic stackup (N=2)

Figure 2. Option "Board Top"

Figure 3. Option "Inside Board with Pad"

Figure 4 .Option "Inside Board no Pad"

Figure 4_1 .Option "Inside Antipad no Pad"

Figure 4_2 .Option "Inside Antipad with Pad"

Figure 4_3 .Option "Inside Board & Antipad with Pad"

Parameters

Name Description Unit Type Default
ID Element ID Text V1
N Number of dielectric layers   1
DV External diameter of via hole Length W[1]
DA Diameter of antipad Length L[1]
DPT Diameter of top capture pad Length L[1]
DPB Diameter of bottom capture pad Length L[1]
TP Thickness of capture pad Length T[1]
H Heights of dielectric layers (vector) Length {0.1 mm}
Er Relative dielectric constants of dielectric layers (vector)   {1}
Rho Via metal bulk resistance relative to gold   1
TopCap Switch "Board Top"/"Inside Board with Pad/Inside Board No Pad/Inside Antipad No Pad"/"Inside Antipad with Pad"/"Inside Board & Antipad with Pad" Length "Board Top"
BotCap Switch "Board Top"/"Inside Board with Pad/Inside Board No Pad/Inside Antipad No Pad"/"Inside Antipad with Pad"/"Inside Board & Antipad with Pad" Length "Board Top"
*Acc Switch "Default/High"   "Default"
*Update_Pad_in_Antipad Switch "No/Yes"   "No"

[1] User-modifiable default. Modify by editing under $DEFAULT_VALUES in the default.lpf file in the root installation directory. See “Default Values” for details.

* indicates a secondary parameter

Parameter Details

N. Defines the number of dielectric layers in a multilayered board separated by ground planes (see the "Basic stackup" figures in the "Topology" section). It is important to note that only layers from the "Basic stackup" are counted toward N. The actual number of layers VIAM uses depends on the options selected with the TopCap and BotCap parameters. Note that VIAM allows a zero value of N (see "Parameter Restrictions and Recommendations".)

DPT, DPB. The diameters of the capture pads attached to the via top end (Port #1) and to the via bottom end (Port #2). Certain TopCap and BotCap parameter options imply that the respective pad is missing.

H, Er. These vector parameters define the height and dielectric constant of every dielectric layer in the board stackup. Note that these vectors always include heights and dielectric constants of layers defined by the TopCap and BotCap parameters. TopCap adds values to the vector head while BotCaps adds values to the vector tail. You must provide correct values for each layer the model uses.

TopCap, BotCap. Each of these switching parameters has six user-selectable options. These options allow the addition of via caps of various configurations to each via end of the basic multilayer configuration presented in the "Basic stackup" figures in the "Topology" section.

TopCap defines the configuration of the via cap at Port #1 and BotCap defines the configuration of the via cap at Port #2.

All configurations of TopCap and BotCap (except "Inside Board no Pad" and "Inside Antipad no Pad" ) assume that a capture pad is present.

Note that TopCap and BotCap can be set independently to different options. The size of vectors H and Er are defined by both selected options.

All available configuration/options are presented in the "Topology" section in figures with corresponding captions. The "Board Top" option requires the addition of one more value to vectors H and Er in addition to the layer values needed for "Basic stackup"; the "Inside Board with Pad " and "Inside Board no Pad" options require the addition of two more values to vectors H and Er; the "Inside Antipad no Pad" option does not add any values to H and Er because it actually leaves the via end "as is" in "Basic stackup. The "Inside Antipad with Pad" and "Inside Board & Antipad with Pad" options insert a capture pad inside the top or bottom antipad; "Inside Antipad with Pad" (as well as "Inside Antipad no Pad") do not add any values to H and Er. The "Inside Board & Antipad with Pad" option requires the addition of one more value to vectors H and Er in addition to the layer values needed for "Basic stackup".

Acc. The default value of the Acc parameter excludes the contribution of higher modes into the via model. Setting Acc=High adds the evaluation of series representing the contribution of higher modes and slightly increases simulation time. In most cases Acc=Default provides sufficient accuracy, but for very long vias crossing many dielectric layers Acc=High might be beneficial.

Update_Pad_in_Antipad. This parameter has an effect only if the TopCaP or BotCap parameter values are either "Inside Antipad with Pad" or "Inside Board & Antipad with Pad". The default value of the parameter Update_Pad_in_Antipad=No neglects the contribution of excess inductance of a pad located inside antipad. Setting Update_Pad_in_Antipad=Yes adds this excess inductance, improving accuracy at higher frequencies but slightly increasing simulation time due to use of the involved numerical algorithms. At lower frequencies (for example, less than 4-5 GHz for a typical PCB) the default value of "Update_Pad_in_Antipad" is sufficient, but at higher frequencies Update_Pad_in_Antipad=Yes might be beneficial.

Parameter Restrictions and Recommendations

  1. The number of layers N in Basic Stackup must be 0<=N<=30. If N=0, then "Basic stackup" is basically a single ground plane with an antipad that separates any of two configurations selected by the TopCap and Bottom cap parameter options. For example, selecting N=0, TopCap="Board Top", and BotCap="Board Top" implements a through via in a two-layer board with a ground plane (containing an antipad) separating adjacent dielectric layers. The lengths of vectors H and Er amount to 2, and you must specify two heights and two dielectric constants. Selecting N=0, TopCap="Board Top", BotCap="Inside Board with Pad" implements a blind via in a three-layer board with a ground plane (containing an antipad) separating the first and second (counting from top) dielectric layers. The length of vectors H and Er amount to 3, and you must specify three heights and three dielectric constants.

  2. This model assumes that only dominant mode TMo propagates in each layer over all frequency sweep. The heights of all layers are checked for normal operation below the cutoff frequency of the higher mode propagating in respective parallel-plate waveguide. If the evaluation frequency exceeds the cutoff threshold, the model generates an error and reports the highest sweep frequency allowed for the specified separation between ground planes.

Implementation Details

The via is modeled as a set of segments contained within ground-separated dielectric layers. Each segment is modeled as a cylindrical antenna dipole radiating between perfectly conducting parallel plates. Modeling techniques used are based on publications [1]-[4]. Via cap capacitance is treated by means of a quasi-static FEM technique based on [5] and [6] Port reference planes are located at the centers of capture pads. Port #1 is associated with the top end of the via and port #2 is associated with the bottom end of the via. The schematic symbol pin marked with a "slash" is associated with Port #1.

Layout

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

Recommendations for Use

The following are examples of various via implementations:

  1. Implementation of through via, N=2

    Figure 5. Via Configuration

    Figure 6. Schematic

  2. Implementation of blind via, N=2

    Figure 7. Via Configuration

    Figure 8. Schematic

  3. Implementation of buried via, N=2

    Figure 9. Via Configuration

    Figure 10. Schematic

  4. Implementation of through via, N=0

    Figure 11. Via Configuration

    Figure 12. Schematic

  5. Implementation of buried via, N=0

    Figure 13. Via Configuration

    Figure 14. Schematic

  6. Series connection of two vias can be implemented if the first VIAM BotCap parameter is "Inside Board with Cap" and the second VIAM TopCap parameter is "Inside Board no Cap". These settings avoid pad doubling.

  7. Sometimes it may be beneficial if a via is connected to a coplanar waveguide line running across the ground plane. To provide this connection set either TopCap or BotCap to "Inside Antipad no Pad". This option sets the via cap as it appears in "Basic stackup" and assumes that capture cap impact at this end is low. To account for pad inside antipad (see the "Topology" section) set TopCap/BotCap either to "Inside Antipad with Pad" or to "Inside Board & Antipad with Pad".

  8. In general, you can create a stack of vias using the two previous recommendations. If the impact of pads inside antipads is neglected, you should select "Inside Antipad no Pad" for stacking; to account for multiple pads inside antipads stack up several VIAMs with N=1 and apply (in turns) Top/BotCap = "Inside Antipad with Pad" and "Inside Antipad no Pad".

  9. This model uses a disk cache, so if a project contains multiple instances of identical VIAM, only one instance simulates and saves results to the cache, and all identical (having the same parameter set) VIAM simply fetch these results from cache. Note that the cache keeps saved data, and any project on the same computer that contains VIAM with the same set of parameters reuses the cached data.

References

[1] Qizheng Gu, Y. Eric Yang, and M.Ali Tassoudji, "Modeling and Analysis of Vias in Multilayered Integrated Circuits," IEEE Trans. on Microwave Theory and Tech., vol. 41, February 1993, pp. 206-214

[2] Qizheng Gu, M.Ali Tassoudji et al, "Coupled Noise Analysis for Adjacent Vias in Multilayered Digital Circuits," IEEE Trans. on Circ. and Syst., vol. 41, December 1994, pp. 796-804

[3] B.Tomasic and A. Hessel, "Linear Array of Coaxially Fed Monopole Elements in a Parallel Plate Waveguide," IEEE Trans. on Antennas and Prop., vol. 36, April 1988, pp. 449-462

[4] M. Goldfarb and R. Pucel, "Modeling Via Hole in Microstrip," IEEE Microwave and Guided Wave Lett., vol. 1, June 1991, pp. 135-137

[5] FEMM (by David Meeker) home page: https://www.femm.info/wiki/HomePage

[6] Jonathan Richard Shewchuk. Triangle. A Two-Dimensional Quality Mesh Generator and Delaunay Triangulator. Follow this link for information and download: http://cs.cmu.edu/~quake/triangle.html

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