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(Obsolete) Simple Volterra FET Model: VFET1


Equivalent Circuit


Name Description Unit Type Default
ID Element ID Text VF1
*GS1 1st volterra coef for controlled source   0.1
*GS2 2nd volterra coef for controlled source   0
*GS3 3nd volterra coef for controlled source   0
*GD1 1st volterra coef for Gds   0.001
*GD2 2nd volterra coef for Gds   0
GD3 3rd volterra coef for Gds   0
*TD Time delay Time 0 ns
*RG Gate resistance Resistance 0.001 ohm
*RS Source resistance Resistance 0.001 ohm
*RD Drain resistance Resistance 0.001 ohm
*RI Intrinsic resistance Resistance 0.001 Ohm
*LG Gate inductance Inductance 0 nH
*LS Source inductance Inductance 0 nH
*LD Drain inductance Inductance 0 nH
*CGS0 PN junction 0V gate capacitance Capacitance 0 pF
*PHI Gate built-in voltage Voltage 1 V
*VGG Gate bias (for Cgs only) Voltage 0 V
*CGD Gate-drain capacitance Capacitance 0 pF
*CGS Gate-source fixed capacitance Capacitance 0 pF
*CDS Drain-source capacitance Capacitance 0 pF
AFAC Gate width scaling factor (total; not per finger)   1
NFING Scale factor for number of gate fingers   1

* indicates a secondary parameter

Implementation Details

The FET's gate-to-source capacitor is modeled by a VCJCN element. The nonlinear controlled current source is modeled by a VVCN element, and the nonlinear drain-to-source resistance by a VGNL . See these elements for further information.


This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

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