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Tapered Via Hole (Closed Form): TVIA



Name Description Unit Type Default
ID Element ID Text V1
D1 Hole diameter at node 1 Length W[1]
D2 Hole diameter at node 2 Length W
H Substrate thickness Length H[1]
T Metal thickness Length T[1]
RHO Metal bulk resistivity normalized to gold   Rho[1]

[1] User-modifiable default. Modify by editing under $DEFAULT_VALUES in the default.lpf file in the root installation directory.

Implementation Details

This component models a tapered cylindrical plated-through via hole. The model is implemented as a lumped element series inductor and resistor whose values are derived from the dimensions and resistivity of the wire.

Recommendations for Use

Discontinuity models function most accurately when attached to lines that match their corresponding edges. Directly connecting discontinuity models to one another reduces their accuracy.


The layout for this cell has hard-coded model layers. When you first use this layout cell, a layer named "TVIA" is added to your drawing layer and model layer list (if they are not already there). Using the model layer mapping, you can assign these layers to draw on any drawing layer. The via is drawn the size of the "D1" parameter.

3D EM Layout

This element has a layout cell specifically for Analyst 3D EM layouts. See “Using 3D EM Elements ” for details on using 3D pCells with Cadence® AWR® Analyst™ 3D FEM EM analysis software.

This model has several layout-only parameters that control how the 3D pCell draws. You access these parameters by selecting the item in the layout, right-clicking and choosing Shape Properties to display the Cell Options dialog box, then clicking the Parameters tab.

Name Value Units Description
NumSideCell 6 Integer Number of sides used to draw the cell, minimum = 4


[1] M.Goldfarb and R.Pucel, "Modeling Via Hole Grounds in Microstrip," IEEE Microwave and Guided Wave Letters., vol. 1, No.6, pp. 135-137.

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