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SSTATZ is a SPICE-equivalent version of the STATZ FET model. It should be used instead of the STATZ model for SPICE compatibility.


Name Description Unit Type Default
ID Device ID Text SF1
*BETA I/V Beta coefficient   0.01
*VTO Threshold (pinch-off) voltage Voltage -2.5 V
*ALPHA Drain I/V knee parameter   2
*LAMBDA Output conductance parameter   0
*THETA I/V parameter (b in Statz's paper)   1
*TAU Gate-drain time delay Time 0 ns
*VBR Gate junction breakdown voltage Voltage 1e+06 V
*IS Gate diode current parameter Current 1e-11 mA
*N Gate diode ideality factor   1
*VBI Gate junction built-in voltage Voltage 1 V
*FC Gate depletion cap. linearization parameter   0.5
*RC RF drain-source resistance Resistance 106 ohm
*CRF Capacitance that determines Rds break frequency Capacitance 0 pF
*RD Drain resistance Resistance 0.001 ohm
*RG Gate resistance; fixed part Resistance 0.001 ohm
*RS Source resistance Resistance 0.001 ohm
*RIN Intrinsic resistance Resistance 0.001 ohm
*CGSO Gate-source capacitance parameter Capacitance 0 pF
*CGDO Gate-drain capacitance parameter Capacitance 0 pF
*NFING Number of fingers scale factor   1
*DELTA2 Capacitance DELTA2 parameter   0.2
*CDS Drain-source capacitance Capacitance 0 pF
*CGS Gate-source fixed capacitance Capacitance 0 pF
*CGD Gate-drain fixed capacitance Capacitance 0 pF
*TNOM Temperature Temperature 27 DegC
*RGD Gate-drain resistance Resistance 0.001 ohm
*LS Source inductance Inductance 0 nH
*LG Gate inductance Inductance 0 nH
*LD Drain inductance Inductance 0 nH
*P Noise par: P    
*Tg Noise par: gate noise temp    
*KF Flicker noise coefficient    
*AF Flicker noise exponent    
*FFE Flicker noise frequency exponent    
*NFLAG Noise model    
AFAC Gate width scale factor   1
VMAX Capacitance limiting voltage Voltage 0.5 V

* indicates a secondary parameter

Implementation Details

The implementation is identical to Staz except for the following charge expressions:



This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

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