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SPICE JFET Model: SJFET

Symbol

Equivalent Circuit

Parameters

Name Description Unit Type Default
ID Device ID Text S1
*VTO Threshold (pinch-off) voltage Voltage -2 V
*BETA I/V BETA parameter   0.0001
*LAMBDA Drain-to-source resistance parameter   0
*RD Drain resistance Resistance 0.001 ohm
*RS Source resistance Resistance 0.001 ohm
*RG Gate resistance Resistance 0.001 ohm
*CGS Gate-source capacitance Capacitance 0 pF
*CGD Gate-drain capacitance Capacitance 0 pF
*PB Gate built-in voltage Voltage 1 V
*IS Gate junction current parameter Current 1e-11 mA
*FC Depletion capacitance linearization parameter   0.5
*T Temperature Temperature 27 DegC
*KF Flicker noise (1/f noise) coefficient    
*AF Flicker noise (1/f noise) exponential term    
*FFE Flicker noise (1/f noise) frequency exponent    
*AFAC Gate-width scale factor   1
*NFLAG Noise model None Spice Model
*BEX Mobility temperature exponent   0
*MJ Grading coefficent for G-S and G-D diodes   0.5
*N Emission coefficent for G-S and G-D diodes   1
*TCV Temperature compensation coefficient for VTO   0
*TNOM Parameter extraction temperature DegC 26.85
*XTI Saturation current temperature exponent    
*COMPAT Model compatibility selector   HSPICE
*LEVEL Model level selector (default=1)    
*LAMBDA1 Gate dependence of channel length modulation parameter    
*EG Energy gap at T=TNOM    
*GAP1 First bandgap correction factor    
*GAP2 Second bandgap correction factor    

* indicates a secondary parameter

Implementation Details

I/V Characteristic

The JFET model is defined for both forward and reverse conduction. The equations for both cases are as follows:

Forward Operation (VDS > 0)

Reverse Operation (VSD = -VDS > 0)

Capacitance

The gate-to-source and gate-to-drain capacitances, Cgs and Cgd, are modeled as PNCAP elements. See PNCAP for the equations.

SCALING

Currents and capacitances are scaled in proportion to AFAC.

All resistances, including gate resistance, are scaled as 1/AFAC.

Gate Diodes

The gate-to-source and gate-to-drain diodes are modeled as PNIV elements. See PNIV for the equations.

NOTE: This model uses a few extra parameters that are not part of the SPICE parameter set. These are necessary for many RF applications. The default values make the model equivalent to the SPICE JFET model.

Layout

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

Reference

[1] P. Antognetti and G. Massobrio, Semiconductor Device Modeling with SPICE, New York: McGraw-Hill, 1988.

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