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Single Shielded CMOS Line (EM Quasi-Static): SIGCMOS

Symbol

Summary

SIGCMOS models single metallic strip of rectangular cross-section located inside the dielectric stack in presence of side and bottom shielding strips. Model allows to remove/install side shields. The structure of model parameters is tailored to standard CMOS process.

Topology

Parameters

Name Description Unit Type Default
ID Element ID Text TL1
W Width of Signal Conductor Length W[1]
WS Width of Side Shield Conductor Length 5 microns
S Spacing between Signal and Side Shield Conductors Length 5 microns
IsSide Side Shield is in Place No/Yes   Yes
SigLev Signal Conductor is on level M7/M6/..M2   M7
BShldLev Bottom Shield Conductor is on level M6/M5/..M1   M6
Nlev Number of Metal Levels   7
L Conductor Length Length L[1]
Acc Accuracy parameter   1
*ErOxide Dielectric Constant of Silicon Oxide   4.1
*TdOxide Loss Tangent of Silicon Oxide   0
*ErPass1 Dielectric Constant of First Top Passivation Layer   3.4
*TdPass1 Loss Tangent of First Top Passivation Layer   0
*ErPass2 Dielectric Constant of Second Top Passivation Layer   7.0
*TdPass2 Loss Tangent of Second Top Passivation Layer   0
*Hpass1 Height (Thickness) of First Top Passivation Layer Length 2.0
*Hpass2 Height (Thickness) of Second Top Passivation Layer (Nitride) Length 0.5
*Hpass3 Height (Thickness) of Third Top Passivation Layer (Oxide) Length 1.0
*Hm7 Stack Height of M7Metal Top Length 17.5
*Hm6 Stack Height of M6 Metal Top Length 11.5
*Hm5 Stack Height of M5 Metal Top Length 5.5
*Hm4 Stack Height of M4 Metal Top Length 4.5
*Hm3 Stack Height of M3 Metal Top Length 3.5
*Hm2 Stack Height of M2 Metal Top Length 2.5
*Hm1 Stack Height of M1 Metal Top Length 1.5
*Tm7 Thickness of M7Metal Length 3.0
*Tm6 Thickness of M6 Metal Length 3.0
*Tm5 Thickness of M5 Metal Length 0.5
*Tm4 Thickness of M4 Metal Length 0.5
*Tm3 Thickness of M3 Metal Length 0.5
*Tm2 Thickness of M2 Metal Length 0.5
*Tm1 Thickness of M1 Metal Length 0.5
*Rho Bulk Resistance of Metallization Relative to Gold   1.47

[1] User-modifiable default. Modify by editing under $DEFAULT_VALUES in the default.lpf file in the root installation directory. See AWR Microwave Office Layout Guide for details.

* indicates a secondary parameter

Parameter Details

IsSide. If this switch is set to Yes side shielding conductors are in place; setting it to No removes side shields and leaves a signal conductor and bottom shield only.

SigLev. This switch allows user to attribute particular metal level to signal conductor and side shields. Placing conductors on certain level provides assignment of Hsig (see Topology) to preset value from available set of stack heights of metal levels; Tsig (see Topology) also gets assigned to predefined thickness value. Actual values of Hsig, Tsig may also be affected by parameter Nlev (see Nlev explanations below).

BShldLev. This switch allows user to attribute particular metal level to the bottom shield conductor. Placing conductors on certain level provides assignment of Hbot (see Topology) to preset value from available set of stack heights of metal levels; Tbot (see Topology) also gets assigned to predefined thickness value. Actual values of Hsig, Tsigmay may also be affected by parameter Nlev (see Nlev explanations below). Model implements sanity checks and checks availability of selected metal levels.

Nlev. Nlev provides actual number of metal levels used in particular CMOS process. Model implies that maximum available number of metal layers is 7 and 4<=Nlev<=7 (content of metal stack for each value of Nlev is shown on Topology). It also implies that elevation of level M7 over M6 and elevation of M6 over M5 is constant for all values of Nlev (in most CMOS processes M7 and M6 are relatively thick metal layers used for power buses and passive high Q elements). Model also implies that all stack heights specified as model parameters are heights of top surfaces of each metal measured from ground plane (see Topology). Thus, changing Nlev changes actual value of Hm5 and actual values of Hm6, Hm7 because any setting Nlev<7 removes one or several metal levels below M5 from the stack (see Topology). Nlev also limits availability of metal level selections done via SigLev and BShldLev. For example, if Nlev=4 than only M7, M6, and M5 are available for SigLev and, correspondingly, only M6, M5, and M4 are available for BshldLev. The table below lists all feasible combinations of metal levels and demonstrates how actual Hm5, Hm6, and Hm7 are evaluated for each value of Nlev.

Nlev Allowed SigLev Allowed BShldLev Actual Hm5 Actual Hm6 Actual Hm7
4 M7, M6, M5 M6, M5, M1 *Hm2 *Hm2+D6 *Hm2+D7
5 M7, M6, M5, M2 M6, M5, M2, M1 *Hm3 *Hm3+D6 *Hm3+D7
6 M7, M6, M5, M3,M2 M6, M5, M3, M2, M1 *Hm4 *Hm3+D6 *Hm4+D7
7 M7, M6, M5, M4, M3, M2 M6, M5, M4, M3, M2, M1 *Hm5 *Hm3+D6 *Hm5+D7

where D6=*Hm6 -*Hm5 and D7=*Hm7 -*Hm5. Asterisk refers to model parameters values.

ErPass1, TdPass1, ErPass2, TdPass2. Model implies that CMOS process protects stack of interconnects with three passivation layers. ErPass1, TdPass1, ErPass2, TdPass2 are material parameters of top two passivation layers counting from top. The third from top passivation layer is silicon oxide.

Hpass1, Hpass2, Hpass3. These parameters are thicknesses (not stack heights) of top three passivation layers.

m1..Hm7. CMOS process specific stack heights of metal levels. Hm1..Hm7 are referenced to the ground plane and measured up to the top of the corresponding metal layer.These parameters are secondary (hidden by default) and must be set to process specific values before modeling.

Tm1..Tm7. CMOS process specific metal thicknesses of metal levels. These parameters are secondary (hidden by default) and must be set to process specific values before modeling.

Rho. Model implies that the same metal is used at all metal levels. Rho is a ratio of metal bulk resistance to bulk resistance of gold. Default value is provided for aluminum.

Parameter Restrictions and Recommendations

  1. Available selections of SigLev and BShldLev are limited to those feasible for the specified Nlev; these restriction may cause error messages if user selects SigLev /BSldLev incompatible with the available set of metal levels (see table on Topology).

  2. The following restrictions must be met: Tbot<0.95Hbot Tsig<0.95(Hsig-Hbot) If they are violated model issues corresponding error messages.

  3. Ground plane location. Model does not account for substrate properties because it is implied that bottom shield effectively isolates signal conductor from substrate influence. Thus, ground plane might be placed at the oxide/substrate boundary.

Implementation Details

Shielding conductors are implied to be connected by vias all the way along the line length and attached to a single port 3. This connection is ideal and vias are not modeled.

Model does not account for silicon substrate properties because it is implied that bottom shield effectively isolates signal conductor from substrate influence.

Width of bottom shield is affected by parameters WS, S even if IsSig=No. Wbottom is always W+2(WS+S) so WS and S might be used to control Wbottom.

Model implementation is based on EM Quasi-Static technique described in [1]. It accounts for losses in metal and in substrate dielectric. Dispersion is partly included

Layout

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

Recommendations for Use

NOTE: The implementation of EM Quasi-Static models relies heavily on the involved numerical algorithms. This may lead to a noticeable increase in simulation time for schematics that employ many such models.

References

[1] M.B. Bazdar, A.R. Djordjevic, R.F. Harrington, and T.K. Sarkar, "Evaluation of quasi-static matrix parameters for multiconductor transmission lines using Galerkin's method," IEEE Trans. Microwave Theory Tech., vol. MTT-42, July 1994, pp. 1223-1228.

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