There is no active replacement for this OBSOLETE element. SIG1LNX models a section of single microstrip line (signal trace) with a conductor strip placed onto the surface of a dielectric layer incorporated into the multilayer dielectric stack (substrate definition NSUB). This model assumes the presence of infinite lateral grounds (backing ground is also modeled) to account for additional return paths in the on-chip environment.
This model is constructed as an X-model (Table Based Interpolation) using the results of an EM 2-D quasi-static cross-sectional analysis based on the Finite Element Method (FEM). For a more detailed discussion of X-models, see “ EM-based Models (X-models) ” . The Quasi-Static FEM technique provides an accurate solution in the presence of a conducting/lossy dielectric stack, at the expense of a longer processor time spent on 2D meshing and solving large systems of linear equations. SIG1LNX gains a computational speed increase due to the table-based interpolation.
SIG1LNX is intended to work within iNets.
SIG1LNX topology is primarily that of NSUB. The first tab of the NSUB Element Options dialog box allows you to create/edit dielectric stackup as well as assign default line parameters to selected dielectric layers. Placing NSUB in the Global Definitions folder (in the Project Browser) provides access to NSUB from both schematics and layout environments.
|W||Width of line||Length||W|
|TL||Line number (assigned in NSUB properties)||1|
|*Sg||Spacing between lateral ground and conductor||Length||W|
|*IsHDL||Switch defines if highly doped layer (HDL) is in place. Choices: No/Yes||No|
|*H_HDL||Thickness of highly doped layer (HDL)||Length||2 microns|
|*Cond_HDL||Bulk conductance of highly doped layer (HDL)||S/m||700|
|*AutoFill||AutoFill DataBase if not equal to 0||0|
 User-modifiable default. Modify by editing under $DEFAULT_VALUES in the
 Modify only if the schematic contains multiple substrates.
* indicates a secondary parameter
W. Conductor width is an independent parameter. This is the actual (modeled) line width; it is not related or associated in any way with the default line width found in NSUB properties (see the following TL parameter details).
TL. The line number. The TL parameter defines the height position of the modeled line in the dielectric stack as well as the material properties of the conductor metal.
The line number must be selected from the "Line #" column of the "Lines" table located on the Stackup tab in the NSUB Element Options dialog box (see "Topology"). You can view NSUB properties by double-clicking the NSUB element on a schematic, or by right-clicking the model name in the bottom window of the Elements Browser and choosing Properties. The Insert, Move up, Move Down, and Remove buttons allow you to create as many lines as needed and place them on top of any layer from a previously created stackup. You create a "Layers" stackup filling table (just above the "Lines" table in the dialog box) by editing cell content as needed and using the Insert and Remove buttons.
SIG1LNX uses TL to get conductor thickness and bulk relative conductance of conductor metal (normalized to gold) from the corresponding cells of the "Lines" table (the model ignores the Default Width column). SIG1LNX also gets the layer number from the same table: SIG1LNX calculates the stackup height (measured up from the stackup bottom) of the top surface of this layer and takes it as stack height of the line conductor bottom.
Certain lines might be located on layers that are off limits for SIG1LNX (see "Parameter Restrictions").
Sg. The secondary parameter. Sg is an independent parameter that defines the offsets of lateral infinitely wide perfect conducting (PEC) grounds (see "Topology"). You can tweak Sg to model the impact of the actual grounding environment.
NSUB. Substrate parameters are listed in the NSUB description. Note that all layers can have arbitrary loss tangent and bulk conductance.
Autofill. A hidden input which allows you to specify that the entire interpolation table should be filled automatically at the current values. To instigate this filling process, this parameter should be set equal to 1. During normal operation, this parameter should be set equal to zero. You can access the hidden parameter by double- clicking on the schematic element.
IsHDL. Parameter IsHDL may take two values: either No or Yes. Default "No" means that no additional (to stack of NSUB) layer is present; "Yes" means that additional layer (presumably, highly doped Si) takes some height down from the top of the bottom layer (it is implied that last layer is a silicon substrate). This layer is not included in dielectric stack defined by NSUB.
H_HDL. Parameter H_HDL represents thickness of additional highly doped layer. If switch IsHDL is set to "No" (default) SIG1LNX ignores this parameter.
Cond_HDL. Parameter Cond_HDL represents bulk conductance of additional highly doped layer in Siemens/meter. If switch IsHDL is set to "No" (default) SIG1LNX ignores this parameter.
SIG1LNX implies that the ratio W/H lies within a predefined range of 0.05 ≤ W/H ≤ 5 and that the ratio Sg/H lies within a predefined range of 0.05 ≤ Sg/H ≤ 10 (H is the total thickness of all dielectric layers stacked above the bottom layer). Outside of this range, this model extrapolates output parameters and issues a warning.
The total thickness of all layers above the line conductor and the total thickness of all layers below the line conductor are fixed parameters; the same as the average dielectric constant and average loss tangent. The relative conductor bulk resistance Rho and the conductor thickness T are also fixed parameters. Cadence® AWR® Microwave Office® software provides pre-generated tables for several typical values of SIG1LNX fixed parameters. Changes to any fixed parameter may start the automatic filling process (if Autofill is set to 1), the length of which may vary. You can change any fixed parameter to create corresponding tables.
The change of line number (TL) causes autofill only if the new line is located on a different stackup layer.
SIG1LNX limits the smallest conductor thickness to 0.1 micron due to possible meshing problems.
SIG1LNX does not accept lines located directly on the surface of the bottom layer, nor lines located on top of the upper layer of the dielectric stack.
A very large spread of thicknesses among layers that comprise the dielectric stack may cause the creation of very large meshes (for example, the number of nodes may exceed 40,000; common meshes contain 2,000 - 5,000 nodes). These huge meshes may slow down autofill and even cause numerical failures. The average autofill times (less than 30 minutes on 2.8 GHz P4) are reached for substrates 100-600 microns thick, and total thickness of silicon oxide 5-15 microns. The thickness of oxide above the conductor and below the conductor should be about 1 micron. It is only the total thickness of the layers above and the total thickness of the layers below the conductor that matter, because actual meshing is applied to this equivalent topology (see "Equivalent Topology").
The actual frequency range for which tables are generated is linked to the first cut-off frequency of the modeled line. This frequency is approximately evaluated as the cut-off frequency of the same line immersed into an oxide stack over a PEC surface. To provide generation of tables valid in the frequency range of a 0-100 GHz model, the total height of oxide above silicon substrate should be in the 5-20 micron range.
SIG1LNX implies that only the bottom layer (substrate) of a dielectric stack has non-zero conductance. Non-zero conductance of any layer above the bottom layer is ignored. Losses of all layers both above and below the line conductor are averaged; the same as dielectric constants. Actually, SIG1LNX reduces a general NSUB structure to a thick lossy conductor sandwiched between two dielectric (presumably, oxide) layers above the third (presumably, silicon substrate) layer (see "Equivalent Topology").
The solution and implementation of FEM quasi-static technology is made possible due to partial use of the FEMM (Finite Element Method Magnetic) code developed by David Meeker . Meshing for FEMM is provided by the Triangle program developed by Jonathan Shewchuk .
This X-model was developed under research performed at Cadence Design Systems, Inc. The full set of details of the implementation are considered proprietary in nature.
This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.
 David Meeker home page: http://femm.foster-miller.net/~dmeeker/ Follow this link for information: http://femm.foster-miller.net/Archives/readme.htm FEMM Manual: http://femm.foster-miller.net/Archives/doc/manual.pdf
 Jonathan Richard Shewchuk. Triangle. A Two-Dimensional Quality Mesh Generator and Delaunay Triangulator. Follow this link for information and download: http://www-2.cs.cmu.edu/~quake/triangle.html