SICAP1 models a stripline interdigital capacitor that connects to striplines without width steps. Model takes advantage of EM Quasi-Static coupled lines approach to consider interaction between all fingers.
|S||Spacing between adjacent fingers||Length||S|
|G||End gap width||Length||S|
|L||Length of the overlap region of the fingers||Length||L|
|N||Number of fingers||4|
|W1||Width of the feeding line at port 1||Length||W|
|W2||Width of the feeding line at port 2||Length||W|
W1, W2. Parameters W1, W2 are read-only (output) parameters, represent the capacitor total width at ports 1 and 2 and are evaluated in the model as N(W+S)-S.
The number of fingers N must be 2≤N≤16.
Conductor thickness is set via substrate parameters. Model doesn't impose restrictions on thickness except requirement to be non-negative.
EM Quasi Static technique allows user to model stripline interdigital capacitor with wide range of conductor thicknesses.
This element uses line types to determine its layout. By default, the layout uses the first line type defined in your Layout Process File (LPF). You can change the element to use any of the line types configured in your process:
Select the item in the layout.
Right-click and chooseto display the Cell Options dialog box.
Click the Layout tab and select a Line Type.
Clickto use the new line type in the layout.
See “Cell Options Dialog Box: Layout Tab ” for Cell Options dialog box Layout tab details.
See “The Layout Process File (LPF)” for more information on editing Layout Process Files (LPFs) and to learn about adding or editing line types.
The model should be used for stripline interdigital capacitors that connect to feeding stripline without width step. If this is not the case and the emphasized metallic strip that connects end of fingers at input ports is present at both sides (or at one side) it is recommended that model SICAP (or SICAP2) is used instead SICAP1. SICAP is geared toward interdigital capacitor that connects to stripline having widths that are small comparing to capacitor width (less than 50% of capacitor width); SICAP2 has width step only at one port.
The model accounts for losses in metal and in substrate dielectric. Dispersion is partly included.
To decrease the calculation time for schematics that contain several stripline interdigital capacitors cache is implemented for this model. It means that during the first evaluation of schematic the most time consuming intermediate parameters for each capacitor instance are being stored in memory cache. Each interdigital capacitor model checks this cache looking for its duplicate. Duplicate capacitors copy the appropriate parameters from memory cache saving substantially on their recalculation.
NOTE: The implementation of EM Quasi-Static models relies heavily on the involved numerical algorithms. This may lead to a noticeable increase in simulation time for schematics that employ many such models.