SICAP models a stripline interdigital capacitor that has an emphasized transverse metallic strip connecting fingers at both input ports. SICAP takes advantage of the EM Quasi-Static coupled lines approach to considering interaction between all fingers.
SICAP$ is the corresponding intelligent cell (iCell). An iCell model is identical to its non-iCell equivalent with the following exception: Certain dimension-related parameters are not explicitly user-specified; rather, they are automatically and dynamically determined by the dimensions of the attached elements. See “Intelligent Cells (iCells)” for a detailed discussion of how to use iCells, their advantages, and their limitations.
|S||Spacing between adjacent fingers||Length||S|
|G||End gap width||Length||S|
|L||Length of the overlap region of the fingers||Length||L|
|N||Number of fingers||4|
|WP||Width of the fingers transverse interconnect||Length||W|
|W1||Width of the feeding line at port 1||Length||W|
|W2||Width of the feeding line at port 2||Length||W|
W1.This parameter is secondary for the SICAP$ iCell model.
W2.This parameter is secondary for the SICAP$ iCell model.
The number of fingers N must be 4≤N≤16. You should use the SICAP1 model instead for all capacitors with N=2 and N=3.
Conductor thickness is set via substrate parameters. SICAP1 does not impose restrictions on thickness except for the requirement to be non-negative.
The EM Quasi-Static technique allows you to model a stripline interdigital capacitor with a wide range of conductor thicknesses.
SICAP1 accounts for the effect of phase shift along the stripline that connects the fingers. It also includes the effect of the presence of width steps at ports.
This element uses line types to determine its layout. By default, the layout uses the first line type defined in your Layout Process File (LPF). You can change the element to use any of the line types configured in your process:
Select the item in the layout.
Right-click and chooseto display the Cell Options dialog box.
Click the Layout tab and select a Line Type.
Clickto use the new line type in the layout.
See “Cell Options Dialog Box: Layout Tab ” for Cell Options dialog box Layout tab details.
See “The Layout Process File (LPF)” for more information on editing Layout Process Files (LPFs) and to learn about adding or editing line types.
You should use this model for stripline interdigital capacitors that have a prominent metallic strip of width WP connecting fingers at both ports. If this is not the case, and one or both widths of feeding lines exceed 50% of the capacitor width, you should use the SICAP1 model. SICAP1 is geared toward interdigital capacitors that are incorporated into stripline having a width equal to that of the capacitor.
This model accounts for losses in metal and in substrate dielectric. Dispersion is partly included.
To decrease the calculation time for schematics that contain several stripline interdigital capacitors, cache is implemented for this model. This means that during the first evaluation of a schematic, the most time-consuming intermediate parameters for each capacitor instance are stored in memory cache. Each interdigital capacitor model checks this cache looking for its duplicate. Duplicate capacitors copy the appropriate parameters from the memory cache, saving substantially on their recalculation.
NOTE: The implementation of EM Quasi-Static models relies heavily on the involved numerical algorithms. This may lead to a noticeable increase in simulation time for schematics that employ many such models.