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Parker-Skellern FET Model: PSFET



The Parker-Skellern FET model is an advanced MESFET model, which may also be useful for HEMTs. It features advanced modeling of dispersion phenomena and derivatives of the I/V characteristic.


Name Description Unit Type Default
*ACGAM Capacitance modulation   0
*BETA Linear-region transconductance scale   0.0001
*CGD Zero-bias gate-drain capacitance Capacitance 0 pF
*CGS Zero-bias gate-source capacitance Capacitance 0 pF
*DELTA Thermal reduction coefficient   0
*FC Forward bias capacitance parameter   0.5
*HFETA High-frequency VGS feedback parameter   0
*HFE1 HFGAM modulation by vGD   0
*HFE2 HFGAM modulation by vGS   0
*HFGAM High-frequency VGD feedback parameter   0
*HFG1 HFGAM modulation by vSG   0
*HFG2 HFGAM modulation by vDG   0
*IBD Gate-junction breakdown current Current 0 mA
*IS Gate-junction saturation current Current 1e-11 mA
*LFGAM Low-frequency feedback parameter   0
*LFG1 LFGAM modulation by vSG   0
*LFG2 LFGAM modulation by vDG   0
*MVST Subthreshold modulation   0
*N Gate-junction ideality factor   1
*P Linear-region power-law exponent   2
*Q Saturated-region power-law exponent   2
*RD Drain ohmic resistance Resistance 0 ohm
*RS Source ohmic resistance Resistance 0 ohm
*TAUD Relaxation time for thermal reduction Time 0 ns
*TAUG Relaxation time for gamma feedback Time 0 ns
*VBD Gate-junction breakdown potential Voltage 1 V
*VBI Gate-junction potential Voltage 1 V
*VST Subthreshold potential Voltage 0 V
*VTO Threshold potential Voltage -2 V
*XC Capacitance pinch-off reduction factor   0
*XI Saturation-knee potential factor   1000
*Z Knee transition parameter   0.5
*RG Gate ohmic resistance Resistance 0 ohm
*LG Gate inductance Inductance 0 nH
*LS Source inductance Inductance 0 nH
*LD Drain inductance Inductance 0 nH
*CDSS Fixed Drain-source capacitance Capacitance 0 pF
AFAC Gate-width scale factor   1
NFING Number of gate fingers scale factor   1
TEMP Simulation temperature Temperature 28.85 DegC
COMPAT Compatibility selector: AWR or ADS   AWR
*CPD Linear gate-drain capacitance Capacitance 0 pF
*CPG Linear gate-source capacitance Capacitance 0 pF
*W Device width Length 1 m

* indicates a secondary parameter

Implementation Details

A new COMPAT parameter is added. This flag allows toggling between two different behaviors, the behavior corresponding to the Cadence® AWR® implementation of the model (COMPAT=AWR) and a new one, the ADS compatibility mode of operation (COMPAT=ADS). Parameters CPD, CPG, and W are only visible in the ADS compatibility mode. Equations are too extensive to list. For more information, see Ref. [1].

Parameter Scaling


This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.


[1] A. Parker and D. Skellern, "A Realistic Large-signal MESFET Model for SPICE," IEEE Trans. Microwave Theory Tech., pp. 1563-1571, Sept. 1997.

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