This element is OBSOLETE and is replaced by the SPICE Level 3 N MOSFET (MOSN3_4A) element. MOSN3_4 is an implementation of the Level 3 MOSFET model developed at the University of California, Berkeley, and used in SPICE2 and SPICE3. The I/V equations are identical to those in SPICE, but the capacitance functions have been modified to eliminate serious discontinuities and implementation problems in harmonic-balance analysis.
MOSN3 and MOSN3_4 differ only in the substrate (bulk) terminal, terminal 4 in the following figure. MOSN3 is a three-terminal model.
The MOSN3and MOSN3_4 models are symmetrical.
Name | Description | Unit Type | Default |
---|---|---|---|
ID | Device ID | Text | M3N1 |
VTO | Threshold voltage at zero bias | Voltage | 0 |
KP | Transconductance parameter | 0 | |
GAMMA | Bulk-effect parameter | 0 | |
PHI | Surface potential | Voltage | 0 |
RD | Drain resistance | Resistance | 0 |
RS | Source resistance | Resistance | 0 |
CBD | Bulk-drain capacitance at zero bias | Capacitance | 0 |
CBS | Bulk-source capacitance at zero bias | Capacitance | 0 |
PB | Bulk junction built-in voltage | Voltage | 0.8 |
IS | Bulk junction current parameter | Current | 10^{-14} |
CGSO | Gate-source overlap capacitance per meter of gate width | Capacitance | 0 |
CGDO | Gate-drain overlap capacitance per meter of gate width | Capacitance | 0 |
CGBO | Gate-bulk overlap capacitance per meter of gate length | Capacitance | 0 |
RSH | Drain & source diffusion sheet resistance | Resistance | 0 |
CJ | Bulk bottom capacitance per square meter at zero bias | Capacitance | 0 |
MJ | Bulk junction grading parameter | 0.5 | |
CJSW | Bulk junction periphery capacitance per meter at zero bias | Capacitance | 0 |
MJSW | Bulk junction periphery capacitance grading parameter | 0.33 | |
JS | Bulk junction saturation current per square meter | Current | 0 |
TOX | Oxide thickness | 0.1 um | |
NSUB | Bulk doping density (cm^-3); must be provided | 0 | |
NSS | Surface state density (cm^-2) | 0 | |
NFS | Fast surface state density (cm^-2) | 0.0 | |
TPG | Gate material flag; aluminum=0, same=-1, diff=+1 | +1 | |
XJ | Metallurgical junction depth | Length | 0 |
LD | Lateral diffusion (L) | Length | 0 |
WD | Lateral diffusion (W) | Length | 0 |
UO | Mobility (cm^{2}/V s); must not be zero if TOX=0 | cm^{2}/Vs | 600 |
VMAX | Max drift velocity | 0 | |
KF | Flicker noise (1/f noise) coefficient) | 0 | |
AF | Flicker noise (1/f noise) exponential term | 0 | |
FFE | Flicker noise (1/f noise) frequency exponent | 1.0 | |
FC | Depletion capacitance linearization parameter | 0.5 | |
XQC | Coefficient of channel charge share | 0.5 | |
DELTA | Width effect on threshold V | 0 | |
THETA | Mobility modulation | 0 | |
ETA | Static feedback | 0 | |
KAPPA | Saturation field factor | 0.2 | |
TYPE | (Not implemented) | NMOS | |
RG | Gate resistance | Resistance | 0 |
RDS | Drain-source resistance | Resistance | 10^{6} |
N | Bulk PN ideality factor | 1 | |
TT | Bulk PN storage time | Time | 0 |
TNOM | Temperature | Temperature | 27 C |
ER | Substrate dielectric constant | 11.7 | |
EOX | Oxide dielectric constant | 3.78 | |
NI | Substrate intrinsic carrier concentration (cm^{-3}) | cm ^{-3} | 1.45*10^{10} |
L | Gate length | Length | 100 um |
W | Gate width | Length | 100 um |
AS | Source diffusion bottom area m^{2} | 0 | |
AD | Drain diffusion bottom area, m^{2} | 0 | |
PS | Source diffusion perimeter | Length | 0 |
PD | Drain diffusion perimeter | Length | 0 |
NRD | Number of squares in drain area (for RD) | 0 | |
NRS | Number of squares in source area (for RS) | 0 |
The Level 3 MOSFET model follows the SPICE implementation. Differences include the following:
Some of the model's default values, listed in SPICE manuals, are not really valid. In particular, the defaults for KP and PHI are calculated; they are not fixed quantities as the documentation sometimes states.
Units in the MW Office implementation of the model may not be the same as SPICE or other implementations. If model parameters are entered from a library, all parameters are in MKS units and there should be no problems.
The Berkeley SPICE3 Level 3 MOSFET model does not include the parameter WD, so it does not modify the gate width; i.e., Weff = W in all cases. We include WD for compatibility with other implementations that do use WD. The latter use the conventional correction, Weff = W - 2 WD.
The Berkeley SPICE3 implementation uses the Meyer capacitance model. This model is severely flawed. It does not conserve charge, has discontinuities that affect both accuracy and convergence, and its integration in SPICE3 is theoretically incorrect. For these reasons, many simulators have implemented the Ward-Dutton model instead of the Meyer model, as has Cadence. This may introduce differences between SPICE3 and Cadence® AWR® Microwave Office® software calculations. For further information on the Ward-Dutton model and on problems of the Meyer model, see Ref. [4]. The Ward-Dutton model is also described in [3], which is the standard reference in the SPICE3 MOSFET model, but the Ward-Dutton model apparently is not implemented in Berkeley SPICE3.
The Level 3 MOSFET model is an old one, developed before there was a sophisticated understanding of the limitations of such models, and suffers from many problems. Most of these are associated with the capacitance model. In some cases, negative gate capacitances can exist, and there can be singularities, at some bias settings. The I/V model has discontinuous derivatives, which also can cause convergence difficulties under some conditions, especially when the device switches between the linear and saturation regions.
Because of these problems, the various implementations of the Level 3 MOSFET model have been customized and are often somewhat different. Wherever discrepancies have occurred, we have attempted to match the HSPICE implementation. If the HSPICE implementation is unclear, we use the Berkeley SPICE3 functions.
This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.
Refs. [1] and [2] have multiple errors, but may be useful for general information. Ref. [3] is the standard for this model, but it implies that the Ward-Dutton capacitance model is used. Ref. [4] presents a good treatment of the model, but it contains typographical errors.
[1] P. Antognetti and G. Maasobrio, Semiconductor Device Modeling with SPICE, McGraw-Hill, New York, 1988.
[2] D. A. Divekar, FET Modeling for Circuit Simulation, Kluwer, Boston, 1988.
[3] A. Vladimirescu and S. Liu, "The Simulation of MOS Integrated Circuits Using SPICE2," Memorandum no. UCB M80/7, Electronics Research Laboratory, University of California, Berkeley, Feb., 1980.
[4] D. P. Foty, MOSFET Modeling with SPICE: Principles and Practice, Prentice Hall, Upper Saddle River, NJ, USA, 1997.
[5] S. Liu, "A Unified CAD Model for MOSFETs," University of California, Berkeley, Memorandum no. UCB/ERL M81/31, 20 May, 1981.