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SPICE Level 1 N MOSFET: MOSN1_4A

Symbol

Summary

This is an N-channel implementation of the SPICE2 MOST (Metal-Oxide-Semiconductor Transistor) LEVEL1 device. The original Meyer capacitance model has been replaced by BSIM1's charge conserving capacitance model. Further enhancements provide support for the most popular Area Calculation Methods, ACM=0 and ACM=2.

Equivalent Circuit

Parameters

Name Description Unit Type Default
ID Element ID Text M1
*VTO Threshold voltage at zero bias V  
*KP Transconductance Parameter    
*GAMMA Bulk-effect parameter    
*PHI Surface potential V  
*LAMBDA Channel-length modulation parameter   0
*RD Drain resistance ohm  
*RS Source resistance ohm  
*CBD Bulk-drain capacitance at zero bias pF  
*CBS Bulk-source capacitance at zero bias pF  
*PB Bulk junction built-in voltage V 0.8
*IS Bulk Junction current parameter   1e-14
*CGSO Gate-source overlap capacitance per meter of gate width   0
*CGDO Gate-drain overlap capacitance per meter of gate width   0
*CGBO Gate-bulk overlap capacitance per meter of gate length   0
*RSH Drain & source diffusion sheet resistance    
*CJ Bulk bottom capacitance per square meter at zero bias    
*MJ Bulk junction grading parameter   0.5
*CJSW Bulk junction periphery capacitance per meter at zero bias   0
*MJSW Bulk junction periphery capacitance grading parameter   0.33
*JS Bulk junction saturation current per square meter   0
*TOX Oxide thickness um 0.1
*NSUB Bulk doping density (cm^-3)   1e15
*NSS Surface state density (cm^-2)   0
*TPG Gate material flag; metal=0, same =-1, diff=+1   1
*LD Lateral diffusion length um 0
*U0 Mobility (cm^2/v*s)    
*FC Depletion capacitance linearization parameter   0
*N Bulk PN ideality factor   1
*NS Sidewall PN ideality factor   1
*TNOM Parameter extraction temperature DegC 26.85
*TEMP Device Temperature DegC 26.85
*KF Drain flicker (1/F) noise coefficient   0
*AF Drain flicker (1/f) noise exponential term   1
*FFE Drain flicker (1/f) noise frequency exponent   1
*L Gate length um 100
*W Gate Width um 100
*AS Source diffusion bottom area m^2    
*AD Drain diffusion bottom area, m^2    
*PS Source diffusion perimeter um  
*PD Drain diffusion perimeter um  
*NRD Number of squares in drain area (for RD)   1
*NRS Number of squares in source area (for RS)   1
*XPART Drain/source channel charge partition in saturation for charge models   1
*NFLAG Noise Model   Noise On
*CAPMOD Capacitance model selector   BSIM1
*MULT Number of devices in parallel   1
*ACM Area calculation method   0
*HDIF Length of heavily doped diffusion um 0
*WMLT Width diffusion layer shrink reduction factor   1
*LDIF Length of lightly doped diffusion 0 um
*SCALM Model scaling factor   1
*XL Length of variation due to masking and etching um 0
*DEL Channel length reduction on both sides um 0
*XW Width variation due to masking and etching um 0
*LMLT Length diffusion layer shrink reduction factor   1
*WD Lateral diffusion length   1
*JSSW Bulk junction saturation current per meter   0

* indicates a secondary parameter

Operating Point Information

The following letter pairs have been used to identify the NL branches: ds, bs, bd, gs and gd

Parameter Description
gm (S) Transconductance .
gmbs (S) Bulk transconductance .
gds (S) Output conductance .
vth (V) Threshold voltage.
vdsat (V) Saturation voltage.
cgg (F) , intrinsic charge.
cgb (F) , intrinsic charge.
cgd (F) , intrinsic charge.
cgs (F) , intrinsic charge.
cbg (F) , intrinsic charge.
cbb (F) , intrinsic charge.
cbd (F) , intrinsic charge.
cbs (F) , intrinsic charge.
cdg (F) , intrinsic charge.
cdb (F) , intrinsic charge.
cdd (F) , intrinsic charge.
cds (F) , intrinsic charge.
csg (F) , intrinsic charge.
csb (F) , intrinsic charge.
csd (F) , intrinsic charge.
css (F) , intrinsic charge.
cjd (F) Drain-bulk junction capacitance.
cjs (F) Source-bulk junction capacitance.
pwr (W) Power at operating point.
gmoverid (1/V) Gm/Ids.
betaeff Effective beta
Isub(A) Substrate current
ro (ohm) Common-source output resistance.
Cgs (F)
Cgd (F)
Cgtot
Cbtot
Cdtot
Cstot
ft (Hz) Unity small-signal current-gain frequency.

Here g, d, s, and b correspond to the intrinsic gate, drain, source and substrate nodes, respectively. These are used to identify branch related operating point information, i.e., branch voltages, currents, etc.

Parameter Details

As with SPICE2 MOST models, parameters can be entered either as electrical parameters or as process parameters, the former used in computing the prior whenever possible. MOSN1_4A accepts empty strings for most parameters.

ACM. The ACM (Area Calculation Method) parameter is used to select the type of diode model used for the MOSFET bulk diodes. In ACM=0 the junction area and perimeter are used in determining the capacitance and reverse saturation current. ACM=2 uses HPSICE-style MOS diodes. This method supports both lightly-doped and heavily doped diffusions, which are described by means of parameters LD, LDIF and HDIF.

CAPMOD. This parameter is used to select the capacitance model. Two models are available: BSIM1 and Meyer's capacitance models. Meyer's capacitance model is only supported in HSPICE simulations.

Implementation Details

This model is mapped into HSPICE as a NMOS M-device with parameters LEVEL and CAPMOD set to 1 and 13, respectively. CAPMOD equal to 13 invokes the BSIM1 charge model.

Equations

The MOS1_4A intrinsic model combines LEVEL1 MOST static and BSIM1 Large-Signal Charge models. The equations for both models are described in detail in Ref. [1]. The small signal model is obtained by linearization of the static and charge large signal model.

Drain-Bulk and Source-Bulk JUNCTIONS

The current and charge contributions from the sidewall and bottom surfaces of each of these junctions are considered separately. These parasitic-diode capacitances and currents are calculated exactly as in SPICE2. See [1] for complete information.

Layout

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

References

[1] P. Antognetti and G. Massobrio, Semiconductor Device Modeling with SPICE, New York: McGraw-Hill, 1988.

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