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SPICE Level 1 3-Terminal N MOSFET: MOSN1A


Implementation Details

This is an implementation of the SPICE 2 MOST (Metal-Oxide-Semiconductor Transistor) LEVEL1 device, where the body (substrate) and source terminals have been connected internally. The original Meyer capacitance model has been replaced by BSIM1's charge conserving capacitance model. Further enhancements provide support for the most popular Area Calculation Methods, ACM=0 and ACM=2. See MOSN1_4A for information on its parameters and implementation.


This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

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