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Philips Level 3100 MOSFET Model: MOS31



The Cadence® MOS31 element implements Philips MOS model 31 level 3100 devices, i.e., mos3100 and mos3100t. The Cadence model implementation is based on the SiMKit 2.2.

MOS Model 31 is a physics based transistor model to be used in circuit simulation and IC-design of analogue high-voltage applications. The model describes the electrical behavior of a junction-isolated accumulation/depletion-type MOSFET. The model is used as the drain extension of high-voltage MOS devices, like the Lateral Double-diffused MOS (LDMOS), the Vertical Double-diffused MOS (VDMOS), and the Extended MOS transistors.

The following physical effects are included in MOS Model 31:

  • Accumulation and depletion underneath the gate oxide

  • Depletion from the substrate (a pn-junction)

  • Pinch-off effects

  • Velocity saturation

  • Temperature scaling

The best reference for the model equations is the Philips website.[1]


Name Description Unit Type Default
ID Element ID Text M1
SELFT Self- Heating flag   off
*TNOM Parameter extraction temperature Temperature 21DegK
*TEMP Device temperature Temperature _TEMP
*MULT Number of devices in parallel   1
*RON Ohmic resistance at zero bias Resistance 1 ohm
*RSAT Space charge resistance at zero bias Resistance 1 ohm
*VSAT Critical drain-source voltage for hot carriers Voltage 10V
*PSAT Velocity saturation coefficient   1
*VP Pinch off voltage at zero gate and substrate voltages Voltage -1V
*TOX Gate oxide thickness Length -1000000m
*DCH Doping level channel (m^ -3)   1e21
*DSUB Doping level substrate (m^ -3)   1e21
*VSUB Substrate diffusion voltage Voltage 0.6V
*VGAP Bandgap voltage channel Voltage 1.2V
*CGATE Gate capacitance at zero bias Capacitance 0nF
*CSUB Substrate capacitance at zero bias Capacitance 0nF
*TAUSC Space charge transit time of the channel Time 0ns
*ACH Temperature coefficient resistivity of the channel   0
*RTH Thermal resistance (K/W)   300
*CTH Thermal capacitance (J/W)   3e-9
*ATH Temperature coefficient of the thermal resistance   0
TYPE Device Type   N

Operating Points

The following letter pairs have been used to identify the NL branches: ds, bs, bd, gs, gb and gd. Here g, d, s and b correspond to the gate, drain, source and substrate terminals, respectively. These are used to identify branch related operating point information, i.e., branch voltages, currents, etc.

Parameter Description
cgg (Capacitance) , intrinsic charge.
cgb (Capacitance) , intrinsic charge.
cgd (Capacitance) , intrinsic charge.
cgs (Capacitance) , intrinsic charge.
cbg (Capacitance) , intrinsic charge.
cbb (Capacitance) , intrinsic charge.
cbd (Capacitance) , intrinsic charge.
cbs (Capacitance) , intrinsic charge.
cdg (Capacitance) , intrinsic charge.
cdb (Capacitance) , intrinsic charge.
cdd (Capacitance) , intrinsic charge.
cds (Capacitance) , intrinsic charge.
csg (Capacitance) , intrinsic charge.
csb (Capacitance) , intrinsic charge.
csd (Capacitance) , intrinsic charge.
css (Capacitance) , intrinsic charge.
Qg Gate terminal charge
Qb Bulk terminal charge
Qd Drain terminal charge
Qs Source terminal charge
pwr (Power) Dissipated power
temp (Temperature) Simulation temperature
u Transistor gain
Rout (Resistance) Small signal output resistance
Vearly (Voltage) Equivalent Early voltage
gm (Conductance) Transconductance
gmb (Conductance) Bulk transconductance
gds (Conductance) Output conductance
Iohm (Current) Drain-source current excluding velocity saturation
Ihc (Current) Critical current for velocity saturation
Vp (Voltage) Channel pinch-off voltage


Implementation Details

The TYPE parameter controls whether the device is N, or, P channel. The extraction and simulation temperatures are controlled using the TNOM and TEMP parameters, respectively; instead of TR and DTA. The SELFT parameter controls whether self-heating modeling is enabled or not. Parameter default and truncation values are identical to those employed by Philips. Operating point information also follows Philip's prescription closely.


This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.



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