MMBCPL models a section of broadside coupled microstrip lines arranged at the two opposite surfaces of a top layer of two-layered substrate. The lower line may be displaced laterally relative to the left edge of the upper line.
|W1||Top conductor width||Length||W|
|W2||Bottom conductor width||Length||W|
|TSwitch||Bottom Conductor Thickness T2= T or T2= -T||T2=T|
|SNAME1||Structure name from lpf file for top conductor||Text||TOP_BCLIN|
|SNAME2||Structure name from lpf file for bottom conductor||Text||BOT_BCLIN|
MSUB2. Two-layer substrate. Parameters are listed in the MSUB2 model description.
Acc. The accuracy parameter. The default value for Acc is 1. If Acc is less than 1 or greater than 10 it is set automatically to 2.
TSwitch. Defines how the bottom conductor protrudes: upward or downward. Direction is defined by a combination of the sign of parameter T and the value of TSwitch. TSwitch="T2=T" T>0 makes both conductors extend their thickness upward; TSwitch="T2=T" and T<0 makes them extend downward. Setting TSwitch="T2=-T" makes the bottom conductor extend the opposite direction relative to the top conductor (if T>0 it extends downward, if T<0 it extends upward.) The default is T>0 and TSwitch="T2=T". See the "Topology" section where two possible layouts are displayed.
Offs. Offs is a relative horizontal offset of the lower line left edge from the left edge of the upper line. Offs may be positive (the lower line is displaced to the right), zero (both lines are aligned) or negative (the lower line is displaced to the left).
Acc is limited to 1≤Acc≤10. A larger value of Acc increases the density of mesh used in computations. The accuracy of model parameters may gain slightly from increasing Acc at the expense of an increase in computation time. Generally, a good trade-off between accuracy and computation time is to set Acc to 1.
MMBCPL does not impose restrictions on conductor thickness (the thickness may be zero, positive, or negative). If thickness parameter T (see the MPSUB parameters) is positive, MMBCPL implies that both strips are leveled up over the corresponding layer boundaries. If T is negative, MMBCPL reassesses the upper strip into the lower layer and extends the lower strip conductor body downward.
Substrate parameters Tand1 and Tand2 (loss tangents for upper and lower layers) should not exceed 3.0; the substrate parameter Sig2 (bulk conductance of the lower layer) should not exceed 3 S/m.
SNAME1 and SNAME2 are for layout only and have no effect on the electrical performance.
Model implementation is based on the EM Quasi-Static technique described in . It accounts for losses in metal and in substrate dielectric. Dispersion is partly included
When you specify SNAME1 and SNAME2, the structures with corresponding names are identified in a $STRUCT_TYPE_BEGIN section of the LPF file. If a structure with the corresponding name is not found, the name of the missing structure is drawn on the error layer. The structure named SNAME1 must contain a text line starting with the line type name used for the top conductor. A structure named SNAME2 must contain a text line starting with the line type name used for the bottom conductor. In a structure named SNAME1=TOP_TRACE and SNAME2= BOT_TRACE with line type names "Top Copper" and "Bot Copper", you need to add the following code to the LPF file (user defined line types may contain any number of layers; structures must contain only one text line):
$LINE_TYPE_BEGIN "Top Copper" ! -> Layer offset minWidth flags "Cu_1" 0 5e-005 0 $LINE_TYPE_END $LINE_TYPE_BEGIN "Bot Copper" ! -> Layer offset minWidth flags "Cu_2" 0 5e-005 0 $LINE_TYPE_END $STRUCT_TYPE_BEGIN "TOP_TRACE" "Top Copper" 0 0 0 $STRUCT_TYPE_END $STRUCT_TYPE_BEGIN "BOT_TRACE" "Bot Copper" 0 0 0 $STRUCT_TYPE_END
Note that text inside structures contains the line type names in quotation marks followed by three blank separated zeros.
MMBCPL may be used to model microstrip line over semiconductor substrate insulated with oxide or another semiconductor. For example, MMBCPL may model microstrip line on SiO2/Si substrate or on GaAs/Si substrate. However, this model imposes limitations on the allowed level of polarization and conductive losses (for instance, only high resistance silicon (HRS) substrates may be modeled).
NOTE: The implementation of EM Quasi-Static models relies heavily on the involved numerical algorithms. This may lead to a noticeable increase in simulation time for schematics that employ many such models.
If the thickness of any layer is too small in comparison to the thickness of another layer, simulation time may also noticeably increase.