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Motorola Electrothermal MOSFET Model: MET_LDMOS

Symbol

Summary

The MET_LDMOS model was developed by Motorola specifically to model LDMOS devices. It includes self-heating.

Equivalent Circuit

Parameters

The following parameters are included in the MET_LDMOS model implemented in the XML library:

Name Description Unit Type Default
ID Element ID Text LD1
*RG_0 Gate resistance at 0C Resistance 1 ohm
*RG_1 Gate resistance temp coef Resistance 0.001 ohm
*RS_0 Source resistance at 0C Resistance 0.1 ohm
*RS_1 Source resistance temp coef Resistance 0.0001 ohm
*RD_0 Drain resistance at 0C Resistance 1.5 ohm
*RD_1 Drain resistance temp coef Resistance 0.0015 ohm
*VTO_0 Threshold voltage at 0C Voltage 3.5 V
*VTO_1 VT temp coef Voltage -0.001 V
*GAMMA IDS parameter   -0.02
*VST Subthreshold slope parameter Voltage 0.15 V
*BETA_0 IDS BETA parameter at 0C   0.2
*BETA_1 BETA temp coef   -0.0002
*LAMBDA IDS parameter   -0.0025
*VGEXP IDS parameter   1.1
*ALPHA IDS parameter   1.5
*VK IDS parameter Voltage 7 V
*DELTA IDS parameter Voltage 0.9 V
*VBR_0 Breakdown V at 0C and Vgs=0 Voltage 75 V
*VBR_1 VBR temp coef Voltage 0.01 V
*K1 Breakdown parameter   1.5
*K2 Breakdown parameter   1.15
*M1 Breakdown parameter   9.5
*M2 Breakdown parameter   1.2
*M3 Breakdown parameter   0.001
*BR Reverse Ids parameter   0.5
*RDIODE_0 Reverse diode series res at 0C Resistance 0.5 ohm
*RDIODE_1 Rev diode temp coef Resistance 0.001 ohm
*ISR Rev diode leakage Current 1e-10 mA
*NR Rev diode ideality   1
*VTO_R Rev diode threshold voltage Voltage 3 V
*RTH Thermal resistance (deg C/W) Resistance 10 ohm
*RDSO Fixed drain-source resistance Resistance 1e+05 ohm
*CDSO Cap in series with Rds0 Capacitance 1e+09 pF
*GGS Gate-source conductance Conductance 100S
*GGD Gate-drain conductance Conductance 100S
*TAU Gate transit time Time 0.001 ns
*TNOM Temp at which parameters were measured Temperature 25 DegC
*TSNK Heat-sink (baseplate) temp Temperature 25 DegC
*CGST CGS temp coef   0.001
*CDST CDS temp coef   0.001
*CGDT CGD temp coef   0
*CTH Thermal capacitance   1
*KF Flicker noise coefficient   0
*AF Flicker noise exponent   1
*FFE Flicker noise frequency exponent   1
*N Forward diode ideality factor   1
*ISS Forward diode leakage   1e-13
*CGS1 Cgs parameter 1 Capacitance 2 pF
*CGS2 Cgs parameter 2 Capacitance 1 pF
*CGS3 Cgs parameter 3 Voltage -4 V
*CGS4 Cgs parameter 4 Capacitance 1 pF
*CGS5 Cgs parameter 5   0.25
*CGS6 Cgs parameter 6   3.5
*CGD1 Cgd parameter 1 Capacitance 0.4 pF
*CGD2 Cgd parameter 2 Capacitance 0.1 pF
*CGD3 Cgd parameter 3   0.1
*CGD4 Cgd parameter 4 Voltage 4 V
*CDS1 Cds parameter 1 Capacitance 1 pF
*CDS2 Cds parameter 2 Capacitance 1.5 pF
*CDS3 Cds parameter 3   0.1
*AREA Area scale factor   1
*N_FING Gate finger scale factor (inverse of the usual def.)   1
*NFLAG Noise model   MET_LDMOS

* indicates a secondary parameter

Implementation Details

The MET_LDMOS model is a new LDMOS model, developed by W. Curtice in cooperation with Motorola (see References). The model includes self-heating, using an electrothermal equivalent circuit.

The model has a number of nice features. The nonlinear capacitances are continuous functions of a single control voltage, eliminating difficulties with discontinuities. Similarly, the drain I/V characteristic is a continuous, infinitely differentiable function. These characteristics are responsible, in part, for the model's robust convergence characteristics.

NOTE

Cadence® has implemented two changes from the description in [2]: (1) the elements RDS0 and CDS0 have been included; and (2) to prevent nonphysical thermal cycling, the default value of CTH is 1.0 F instead of zero.

The definition of N_FING is unusual; it is the ratio of the number of gates of the standard device to the number of gates of the scaled device:

N_FING is the inverse of the gate-scaling parameter used in most of the other models. The definition of AREA is the conventional one, however:

Equations

The model equations are too extensive to be repeated here; Ref. [2] is the standard documentation for the model.

Layout

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

References

[1] W. Curtice, J. Pla, D. Bridges, T. Liang, and E. Shumate, "A New Dynamic Electro-Thermal Nonlinear Model for Silicon RF LDMOS FETs," IEEE International Microwave Symposium Digest of Papers, 1999.

[2] Motorola's Electro Thermal (MET) LDMOS Model, Motorola Internal Report. (No identifying numbers or date; available by download from http://www.nxp.com/products/rf/rf-high-power-models:RF_HIGH_POWER_MODELS_HOME_PAGE.)

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