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Modified Materka FET Model: MATRK

Symbol

Equivalent Circuit

Parameters

Name Description Unit Type Default
ID Device ID Text MF1
*IDSS Drain saturation current at zero Vgs Current 100 mA
*VP Pinch-off voltage Voltage -2 V
*GAM Pinch-off slope parameter   0
*E Constant part of gate I/V exponent   2
*KE Dependence of power law on Vgs   0
*SL Slope of drain I/V in linear region   0.15
*KG Drain Vgs dependence in linear region   0
*SS Slope of drain I/V in saturation   0
*T Gate-drain time delay Time 0 ns
*IG0 Saturation current of GS diode Current 0 mA
*AFAG Exponential coef of GS diode   38.7
*IB0 Saturation current of GD diode Current 0 mA
*AFAB Exponential coef of GD diode   38.7
*VBC Breakdown voltage Voltage 1e+06 V
*R10 Intrinsic resistance Resistance 0.001 ohm
*KR (Not implemented)   0
*C10 Cgs at zero voltage Capacitance 0 pF
*K1 Inverse of built-in voltage for G-D cap.   1.25
*C1S Constant part of Cgs Capacitance 0 pF
*CF0 Cgd at zero voltage Capacitance 0 pF
*KF Inverse of built-in voltage for G-D cap.   1.25
*RS Source resistance Resistance 0.001 ohm
*RG Gate resistance Resistance 0.001 ohm
*RD Drain resistance Resistance 0.001 ohm
*P Noise par: P   2
*Tg Noise par: gate noise temp Temperature 16.85
*NKF Flicker noise coefficient   0
*AF Flicker noise exponent   1
*FFE Flicker noise freq. exponent   1
*NFLAG Noise model   AWR1
*NFING No. of fingers scale factor   1
AFAC Gate-width scale factor   1

* indicates a secondary parameter

Implementation Details

I/V Characteristic

where

Capacitance

Parameter Scaling

Cgs, Cgd, and the currents Ids, Igs, and Igd are scaled in proportion to AFAC.

Layout

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

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