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Philips JUNCAP Model: JUNCAP

Symbol

Summary

The JUNCAP model is appropriate for characterizing the behavior of diodes formed by the source, drain, or well-to-bulk junctions in MOST devices. The model is limited to the case of reverse biasing of these junctions. The currents contributions from the sidewall, bottom, and gate-edge-junctions are considered separately. This allows to include the effects resulting from differences in the junction doping profiles. Accordingly, the equivalent circuit is comprised of three diode-like current sources in parallel, one for each of the junctions. Both the diffusion and the generation currents are considered in the model, each with its own temperature and voltage dependence.

Parameters

Name Description Unit Type Default
ID Device ID Text PN1
*TNOM Parameter extraction temperature DegC 25
*TEMP Device temperature DegC 25
*MULT Number of devices in parallel   1
*AB Diffusion area (m^2)   1e-12
*LS Side-wall length which is not under gate um 1
*LG Side-wall length under gate um 1
*VR Parameter value reference voltage V 0
*JSGBR Bottom saturation current density due to electron-hole generation (A m^-2)   0.001
*JSDBR Bottom saturation current density due to diffusion from back-contact (A m^-2)   0.001
*JSGSR Side-wall saturation current density due to electron-hole generation (A m^-2)   0.001
*JSDSR Side-wall saturation current density due diffusion from back-contact (A m^-2)   0.001
*JSGGR Gate-edge saturation current density due to electron-hole generation (A m^-2)   0.001
*JSDGR Gate-edge saturation current density due diffusion from back-contact (A m^-2)   0.001
*NB Bottom forward current emission coefficient   1
*NS Side-wall forward current emission coefficient   1
*NG Gate-edge forward current emission coefficient   1
*VB Reverse breakdown voltage V 0.9
*CJBR Bottom junction capacitance (Fm^-2)   1e-12
*CJSR Side-wall junction capacitance (Fm^-2)   1e-12
*CJGR Gate-edge junction capacitance (Fm^-2)   1e-12
*VDBR Bottom junction diffusion voltage V 1
*VDSR Side-wall junction diffusion voltage V 1
*VDGR Gate-edge junction diffusion voltage V 1
*PB Bottom junction grading coefficient   0.4
*PS Side-wall junction grading coefficient   0.4
*PG Gate-edge junction grading coefficient   0.4

* indicates a secondary parameter

Parameter Details

The default and restrictions on the range of parameter values is in full compliance with the model definition.

Implementation Details

This model is mapped into HSPICE as a LEVEL 4 D-device. For the complete set of equations see Ref [2].

Layout

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

References

[1] Philips Semiconductor web site, http://www.semiconductors.philips.com/Philips_Models/additional/juncap/.

[2] Philips Semiconductor web site, http://www.semiconductors.philips.com/Philips_Models/additional/m_juncap/.

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