Name | Description | Unit Type | Default |
---|---|---|---|

ID | Device ID | Text | FF1 |

*P1 | Gate I/V polynomial coefficient | 1 | |

*P2 | Gate I/V polynomial coefficient | 0 | |

*P3 | Gate I/V polynomial coefficient | 0 | |

*P4 | Gate I/V polynomial coefficient | 0 | |

*P5 | Gate I/V polynomial coefficient | 0 | |

*P6 | Gate I/V polynomial coefficient | 0 | |

*VPK0 | Gate voltage at peak Gm | Voltage | 0 V |

*IPK | Current at peak Gm | Current | 50 mA |

*DEL1 | Drain I/V polynomial coefficient | 0 | |

*DEL2 | Drain I/V polynomial coefficient | 0 | |

*DEL3 | Drain I/V polynomial coefficient | 0 | |

*DEL4 | Drain I/V polynomial coefficient | 0 | |

*DEL5 | Drain I/V polynomial coefficient | 0 | |

*DEL6 | Drain I/V polynomial coefficient | 0 | |

*GAMMA | Drain I/V knee parameter | 0 | |

*ALP0 | Drain I/V knee parameter | 1 | |

*ALP1 | Drain I/V knee parameter | 0 | |

*LAMBDA0 | Drain-source resistance parameter | 0 | |

*LAMBDA1 | Drain-source resistance parameter | 0 | |

*TAU | Gate-drain time delay | Time | 0 ns |

*CGS0 | Gate capacitance parameter (per mm of width) | Capacitance | 0.25 pF |

*CF | Gate capacitance term | Capacitance | 0.15 pF |

*GCG | Gate capacitance term | Capacitance | 0.2 pF |

*DCG | Gate capacitance range term | Voltage | 2.7 V |

*DKGS | Gate capacitance knee term | Voltage | 3 V |

*IG0F | Gate diode forward current parameter | Current | 1e-17 mA |

*ALPGF | Gate diode forward exponential parameter | 40 | |

*PB1 | Gate breakdown polynomial coefficient | 1 | |

*PB2 | Gate breakdown polynomial coefficient | 0 | |

*PB3 | Gate breakdown polynomial coefficient | 0 | |

*PB4 | Gate breakdown polynomial coefficient | 0 | |

*PB5 | Gate breakdown polynomial coefficient | 0 | |

*PB6 | Gate breakdown polynomial coefficient | 0 | |

*VGSPK | Gate voltage peak for breakdown | Voltage | -1 V |

*IG0R | Gate diode breakdown current parameter | Current | 0.001 mA |

*ALPGR | Gate diode breakdown exponential parameter | 40 | |

*BVGDPK | Drain-to-gate breakdown voltage | Voltage | 1e+06 V |

*RG | Gate resistance | Resistance | 1 ohm |

*RS | Source resistance | Resistance | 1 ohm |

*RGS | Intrinsic resistance | Resistance | 1 ohm |

*RD | Drain resistance | Resistance | 1 ohm |

*RGD | Gate-drain resistance | Resistance | 1 ohm |

*RDSF | RF drain-source resistance | Resistance | 300 ohm |

*CDSF | Capacitance that determines Rds break frequency | Capacitance | 0 pF |

*CDS | Drain-source capacitance | Capacitance | 0 pF |

*CPDS | Drain-source pad capacitance (not scaled) | Capacitance | 0 pF |

*CPGS | Gate-source pad capacitance (not scaled) | Capacitance | 0 pF |

*CPGD | Gate-drain pad capacitance (not scaled) | Capacitance | 0 pF |

*LS | Source inductance | Inductance | 0.001 nH |

*LG | Gate inductance | Inductance | 0.001 nH |

*LD | Drain inductance | Inductance | 0.001 nH |

W | Gate width, mm (affects only Cgs & Cgd) | 1 | |

AFAC | Gate width scale factor | 1 | |

NFING | Number of fingers scale factor | 1 |

`* indicates a secondary parameter`

This models offers a capacitance function whose parameters are relatively easy to extract, an improved breakdown model, and an improved I/V model. It is loosely based on the Angelov (Chalmers) model. This model is designed to reproduce the I/V derivatives correctly; thus, with proper parameter extraction, it should be useful for intermodulation analysis.

The drain current is given by

where

The above expressions are defined for V_{d} > 0. When
V_{d} < 0,

The current sources Igs and Igd account for both gate rectification
and breakdown. The expressions for both sources are identical. In
forward conduction (V_{g} > 0 or V_{gd} > 0), the
current is given by the diode junction equation:

The breakdown current (-V_{gd} > V_{bd} or -V_{gs} > V_{bg}) is
given by

where V_{bg}, V_{bd} are positive quantities and

The gate-to-source and gate-to-drain charge functions are symmetrical. They are given by the following expressions:

Because of the symmetry, one function can be used for both charges.

Resistances, channel current, and linear capacitances are scaled in the standard manner:

Resistances are scaled as 1/AFAC;

Gate resistance, RG, is scaled as AFAC/NFING^{2};

Capacitances are scaled in proportion to AFAC.

Scaling of the nonlinear channel capacitance, C_{g}, is
different from other MW Office models.

W is the device width in mm, and CGS0 is the capacitance per mm. This capacitance is proportional to W; it is not scaled by AFAC. If CGS0 is provided as the total capacitance of a particular device, it is correct simply to enter that capacitance for CGS0 and set W = 1 for the standard device. Then, to scale the device, set W = AFAC. W affects no other model parameters.

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

[1] K. Fujii, Y. Hara, F. M. Ghannouchi, T. Yakabe, and H. Yabe, "A Nonlinear GaAs FET Model Suitable for Active and Passive MM-Wave Applications," IEICE Trans., vol. E83-A, no. 2, p. 228, Feb., 2000.

[2] K. Fujii, K. Ogawa, and Y. Takano, "The Consideration of Voltage-Controlled Charge Sources Controlled by Two Voltage Sources for a GaAs MESFET Large-Signal Model," IEIEC Trans., vol. J80-C-I, no. 9, p. 414, Sept. 1997.

[3] K. Fujii, Y. Hara, T. Yakabe and H. Yabe, "Accurate Modeling for Drain Breakdown Current of GaAs MESFETs," IEEE Trans. Microwave Theory Tech., vol. 47, no. 4, p. 516, April, 1999.