DIFRIND models a rectangular differential microstrip inductor/transformer with a center tap. This model is based on an evaluation of self and mutual inductances, capacitances and resistances between all parallel segments; this evaluation is based on an accurate quasi-static model of an arbitrary number of edge-coupled microstrip lines. The center tap is implemented as an underpass bridge that is common for GaAs designs. A differential inductor may replace two inductors joined by a common AC ground in differential amplifier or oscillator circuits.
|N||Number of turns(>=3, odd value only)||3|
|L1||Size of inductor horizontal side (w/ cross-over gap)||Length||80 um|
|L2||Size of inductor vertical side (w/o cross-over gap)||Length||155 um|
|W||Width of inductor windings||Length||10 um|
|S||Spacing between inductor windings||Length||5 um|
|Z||Gap for cross-over between windings||Length||20 um|
|TU||Thickness of underpass metal||Length||1 um|
|RhoU||Underpass metal bulk resistivity normalized to gold||1|
|WU||Width of underpass||Length||10 um|
|HU||Height of dielectric above underpass||Length||1 um|
|LU||Length of underpass extension beyond inductor outline||Length||0 um|
|PU||Length of underpass horizontal shoulder||Length||30 um|
|DU||Length of underpass vertical shoulder that extends beyond inductor outline||Length||15 um|
|ErU||Relative dielectric constant of dielectric above underpass||1|
|TandU||Loss tangent of dielectric above underpass||0|
* indicates a secondary parameter
N. The number of turns/windings forming the differential inductor. Actually, the differential inductor comprises two connected sub-inductors; each winding comprises two halves, each belonging to a different sub-inductor. Sub-inductors connect at port #3. The number of windings N is limited to odd values only and must be greater or equal to 3. This model runs a layout feasibility check before performing calculations.
Acc. The accuracy parameter. The default value for Acc is 1. If Acc is less than 1 or greater than 10 it is set automatically to 1.
N takes only odd values. Even values of N result in a layout that differs from the layout assumed for the current implementation of DIFRIND: This happens because even N mandates the location of port 3 at the same side of the inductor where ports 1 and 2 are located (odd N places port 3 at the opposite side). The proximity of all ports makes GaAs (and similar technologies) design relatively complicated; it also may result in undesirable stray coupling between inputs.
This model checks the underpass horizontal shoulder width PA to verify it is small enough to contact the top of the innermost winding (see "Topology") and if PA is large enough to prevent the underpass vertical shoulder to span the cross-over gap Z (see "Topology").
This model checks the sizes of internal openings because you may specify N, W, and S so that all windings cannot be squeezed into dimensions L1 and/or L2.
The Accuracy parameter Acc is limited to 1 ≤ Acc ≤ 10 . A larger value of Acc increases the density of mesh used in computations. The accuracy of model parameters may gain slightly from increasing Acc at the expense of a noticeable increase in computation time. Generally, a good trade-off between accuracy and computation time is to set Acc to 1.
To decrease the calculation time for schematics that contain several DIFRIND inductors, cache is implemented for this model. This means that during the first evaluation of a schematic the most time-consuming intermediate parameters (characteristics of coupled lines) for each inductor instance are stored in the disk cache. Each inductor model checks this cache looking for its duplicate. Duplicate inductors copy the appropriate parameters from the disk cache, saving substantially on their recalculation.
Note that the model caches only frequency-independent characteristics of coupled lines, but recalculates the large equivalent circuit network (derived from coupled line characteristics) at each swept frequency. Thus, if the number of swept frequency points is large (say, 300) the total time spent on equivalent circuit evaluation may substantially exceed the time for evaluation of coupled line characteristics. In this particular case, time saving due to caching may be relatively moderate.
NOTE: The implementation of EM Quasi-Static models relies heavily on the involved numerical algorithms. This may lead to a noticeable increase in simulation time for schematics that employ many such models.
This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.