CPW2LINA models a section of two asymmetric coupled coplanar waveguides (strip widths may be unequal and gaps between each strip conductor and closest lateral ground may have unequal width) on dielectric substrate. This model accounts for an optional metallic cover, an optional backing ground plane, and allows for arbitrary metal thickness of the signal conductor and lateral ground planes.
|W1||Conductor 1 width - nodes 1&3||Length||W|
|W2||Conductor 2 width - nodes 2&4||Length||W|
|S1||Gap width Gnd & conductor 1||Length||W|
|S2||Gap width conductor 1&2||Length||W|
|S3||Gap width conductor 1 & Gnd||Length||W |
 User-modifiable default. Modify by editing under $DEFAULT_VALUES in the
 If only one CPW_SUB is present in the schematic, this substrate is automatically used. If multiple CPW_SUB substrate definitions are present, the user must specify.
CPW_SUB. Supplies parameters for dielectric substrate, conductor thickness, conductor metal properties, the presence/absence of metallic cover/backing, and the cover height over the substrate. The Cover and Gnd parameters allow the addition/elimination of infinite metallic plates acting as a cover or grounded backing. The CPW2LINA model does not use the following CPW_SUB parameters: Hab, ER_Nom, H_Nom, Hcov_Nom, Hab_Nom, and T_Nom.
Acc. The accuracy parameter. The default value for Acc is 1. If Acc is less than 1 or greater than 10 it is set automatically to 2.
The Acc parameter A is limited to 1<Acc>10. A larger value of Acc increases the density of mesh used in computations. The accuracy of model parameters may improve slightly by increasing Acc, at the expense of a noticeably longer computation time. Generally, a good trade-off between accuracy and computation time is to set Acc to 1.
This model does not impose restrictions on the conductor thickness (thickness may be zero, positive, or negative). Negative thickness means that the conductor is recessed into the substrate.
Model implementation is based on the EM Quasi-Static technique described in . It accounts for losses in metal and in substrate dielectric. Dispersion is partly included.
Setting Gnd=0 implies that the substrate is not backed by a perfect conductor, but is bounded by infinite air space. Modeling results are strongly affected by thin substrate heights and might differ substantially from modeling results obtained from models that implement the common conception of coplanar waveguide. To model classic coupled coplanar waveguides featuring infinitely thick substrate, set Gnd=0 and H >2(W1+W2+S1+S2+S3), where Gnd and H are parameters of CPW_SUB.
To apply Method of Moments for analysis, a quasi-static model creates 1D mesh covering contours of all conductors. The mesh is made of linear segments (pulses) of varying length. The length of a pulse is relatively big at the conductor center; it decreases toward conductor edges to reveal the charge distribution across conductor. If the conductor width is too large it may cause the pulse size to approach zero for pulses close to edge. In these rare cases the model may display a “Length of pulse #nnn equal to zero” error message.
This element uses line types to determine its layout. By default, the layout uses the first line type defined in your Layout Process File (LPF). You can change the element to use any of the line types configured in your process:
Select the item in the layout.
Right-click and chooseto display the Cell Options dialog box.
Click the Layout tab and select a Line Type.
Clickto use the new line type in the layout.
See “Cell Options Dialog Box: Layout Tab ” for Cell Options dialog box Layout tab details.
CPW elements have special configurations for the defined line types. The center conductor geometry draws on all the layers defined in the line type. The spacing to the ground plane is then drawn on negative layers with the same name as all of the layers in the line type. You must then draw the same layers on the positive layer to complete CPW layout. See “Negative Layers ” for more information on setting up processes for positive and negative layers.
See “The Layout Process File (LPF)” for more information on editing Layout Process Files (LPFs) and to learn about adding or editing line types.
NOTE: The implementation of EM Quasi-Static models heavily relies on the involved numerical algorithms. This may lead to a noticeable increase in simulation time for schematics that employ many such models.
If the thickness of any layer is too small in comparison with the thickness of another layer, simulation time may also noticeably grow.