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The Cadence® BSIMOI element is a MOSFET model for SOI (Silicon-On-Insulator) circuit design. This model is formulated on top of the BSIM3 framework. It shares the same basic equations with the bulk model so that the physical nature and smoothness of BSIM3v3 are preserved. BSIMSOI is Verilog-A based and implements version 4.4.

See the BSIM model website[1] for complete documentation and Verilog-A definition of component models.


Only primary parameters are shown. Secondary parameters follow the BSIMSOI model specification/standard.

Name Description Binnable Unit Type Default
ID Element ID   Text X1
VERSION Version selector     4.4
TYPE Device type     NMOS
TERMS Number of terminals exposed     g d s e p
TNOM Temperature at which params were extracted   Temperature 27
TEMP Ambient temperature   Temperature _TEMP

Operating Points

You can access operating point information, as defined by the active Verilog-A based component model.

Implementation Details

This model is only supported for AWR® APLAC® HB simulator measurements.

The TYPE parameter controls whether the device is NMOS or PMOS and the TERMS parameter controls which terminals are exposed. You can select five different values: "g d s", "g d s e", "g d s e p", "g d s e p b", and "g d s e p b t". The terminal names are the same as those used in the Verilog-A definition of the model. The current setting of any of these parameters is reflected by the device symbol. The extraction and simulation temperatures are controlled using the TNOM and TEMP parameters, respectively. Parameter default and truncation values are identical to those found in the Verilog-A definition of the model.


This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.


[1] http://www-device.eecs.berkeley.edu/bsim/

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