Go to www.awrcorp.com
Back to search page Click to download printable version of this guide.

BSIMS6 MOSFET Model: BSIM6

Symbol

Summary

The Cadence® BSIM6 element implements the latest bulk MOSFET model from the BSIM Group. "The model provides excellent accuracy compared to measured data in all regions of operation. It features model symmetry valued for analog and RF applications while maintaining the strong support and performance of the BSIM model valued for all applications since 1996." BSIM6 is Verilog-A based and implements version 1.0.

See the BSIM6 model website[1] for complete documentation and Verilog-A definition of component models.

Parameters

Only primary parameters are shown. Secondary parameters follow the BSIM6 model specification/standard.

Name Description Binnable Unit Type Default
ID Element ID   Text X2
VERSION Version selector     1.0
TYPE Device type     NMOS
TNOM Temperature at which params were extracted   Temperature 27
TEMP Ambient temperature   Temperature _TEMP
GEOMOD Geo dependent parasitics model     0
RGEOMOD Geometry-dependent source/drain resistance     0
COVMOD Use Bias-independent Overlap Capacitances     0
RDSMOD Internal s/d resistance model     0
GIDLMOD Turn off GIDL Current     0
RGATEMOD Gate resistance model selector     0
RBODYMOD Distributed body R model     0
IGCMOD Turn off Igc, Igs and Igd     0
IGBMOD Turn off Igb     0
TNOIMOD Thermal noise model selector     0
NF Number of fingers     1
PERMOD Whether PS/PD (when given) include gate-edge perimeter     1
MINZ Minimize either D or S     0
NGCON Number of gate contacts     1

Operating Points

Operating point information is identical to that found in the Verilog-A definition of the model.

Implementation Details

This model is only supported for AWR® APLAC® HB simulator measurements. The TYPE parameter controls whether the device is NMOS or PMOS. The extraction and simulation temperatures are controlled using the TNOM and TEMP parameters, respectively. Parameter default and truncation values are identical to those found in the Verilog-A definition of the model.

Layout

This element does not have an assigned layout cell. You can assign artwork cells to any element. See “Assigning Artwork Cells to Layout of Schematic Elements” for details.

References

[1] https://awrcorp.com/support/help.aspx?id=55

Legal and Trademark Notice