This error occurs when a wave port is incorrectly defined. Only conductors are identified on the port surface; no dielectrics. Either no dielectric material is defined on the port plane, or the dielectric material is electrically isolated from the conductor. Without the dielectrics, no modes can be defined during the wave port solve.
To fix this error, verify that material properties are applied correctly and that there is no unintended gap between the port face and its adjacent dielectric. Any such gap is treated as an outer PEC boundary and isolates the dielectric from port face if the gap exists outside of the simulation enclosure. The default boundary condition for unassigned exterior faces is PEC.
This error can occur with an improperly drawn coaxial line. In the following figures, the coaxial line extends outside of an Analyst boundary shape, therefore the default boundary around the line is PEC. In the example, only the inner and outer conductors are drawn; no insulator is drawn. In this case, there is no dielectric defined, and the space that the insulator would have occupied is assigned the default PEC boundary condition.
In the following figure, the inner conductor of the coax protrudes beyond the insulator. There is no dielectric defined on the plane of the port face, and the insulator is shorted-out by the default PEC boundary condition.
In the final figure, there is a gap between the inner conductor and insulator. This gap is considered an exterior boundary, and treated as the default PEC boundary condition. Again, the inner conductor is isolated from the insulator by the background PEC boundary condition. In this figure, the gap is exaggerated so it is easily seen. It is possible for the gap to be very small and only visible after zooming around the edge of the inner conductor.
For more information about Analyst ports, see ports.